\doxysubsubsection{RCCEx Exported Macros }
\hypertarget{group___r_c_c_ex___exported___macros}{}\label{group___r_c_c_ex___exported___macros}\index{RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection*{Topics}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_r_s___extended___features}{RCCEx CRS Extended Features}}
\end{DoxyCompactItemize}
\doxysubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gacc1a8ad328f57e3dcade01e5355e0add}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Macros to enable or disable PLL2. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga1e44121d27a8d6096c170d4a2e7c1981}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gadee20de14af30b0f958fda51d852066b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+CLKOUT\+\_\+\+ENABLE}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+Clock\+Out\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Enables or disables each clock output (PLL2\+\_\+\+P\+\_\+\+CLK, PLL2\+\_\+\+Q\+\_\+\+CLK, PLL2\+\_\+\+R\+\_\+\+CLK) \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga20869ea15ad0f090d4e3fcc217242474}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+CLKOUT\+\_\+\+DISABLE}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+Clock\+Out\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga25e0f4d0ef5f525a3c0c5c0a155d0ac6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+FRACN\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga320b2becbdbe9830622f1b96526a5d7b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+FRACN\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga1b17f7d45a505cc6acce76a1a80d9aca}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+PLL2\+M\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLL2\+N\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLL2\+P\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLL2\+Q\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLL2\+R\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configures the PLL2 multiplication and division factors. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gac2cb75d60618ffea824634490f9d81eb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+FRACN\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+FRACN\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga88d12a5c64e4a820268b9f7f50d74179}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+\_\+\+VCIRANGE}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+VCIRange\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to select the PLL2 reference frequency range. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga5b448c0dab856525467ba9146db00432}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+\_\+\+VCORANGE}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+VCORange\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to select the PLL2 reference frequency range. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gac7c3a26323f470a939b021ad76f29518}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Macros to enable or disable the main PLL3. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga9eccd5f7fbfd12da15ba7d76d9a21d18}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga35af940f02bf692f69ca9cf2dd598f24}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+FRACN\+\_\+\+ENABLE}}()
\begin{DoxyCompactList}\small\item\em Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga4a2fb65aefcf9fd35d55a5de8000173e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+FRACN\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga44dba3c4e64245e760eb3e780096b4da}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+CLKOUT\+\_\+\+ENABLE}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+Clock\+Out\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Enables or disables each clock output (PLL3\+\_\+\+P\+\_\+\+CLK, PLL3\+\_\+\+Q\+\_\+\+CLK, PLL3\+\_\+\+R\+\_\+\+CLK) \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga36d6e5c5786cab7644e5149d00f704c3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+CLKOUT\+\_\+\+DISABLE}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+Clock\+Out\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gac5020a08025c53436a32d77640786d5d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+PLL3\+M\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLL3\+N\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLL3\+P\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLL3\+Q\+\_\+\+\_\+,  \+\_\+\+\_\+\+PLL3\+R\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configures the PLL3 multiplication and division factors. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga3c6bb3051b93d8f3051ace7b1611c5c1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+FRACN\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+FRACN\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configures PLL3 clock Fractional Part of The Multiplication Factor. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga5825c7707fdbf1432a215fbf3ef4b766}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+\_\+\+VCIRANGE}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+VCIRange\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to select the PLL3 reference frequency range. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga7c53c8f29406ecd9c45434db4b2af32d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+\_\+\+VCORANGE}}(\+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+VCORange\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to select the PLL3 reference frequency range. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga0c98df7eb7d710df2bf05427a4a10bc7}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RCC\+\_\+\+SAI1\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to Configure the SAI1 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga9af45dae7c2f2f1c8848be68d7bded7e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SAI1\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the SAI1 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga6cf17efbf8f472437732901308320283}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPDIFRX\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RCC\+\_\+\+SPDIFCLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to Configure the SPDIFRX clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gad3ddc626288e3b401da0b8547f2ac0d3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPDIFRX\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the SPDIFRX clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gafd775b802b35eddc3763819b696c8dc6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1235\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+I2\+C1235\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em macro to configure the I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock (I2\+C123\+CLK). \end{DoxyCompactList}\item 
\Hypertarget{group___r_c_c_ex___exported___macros_ga1c11406787c87ef39597619fae00bd88}\label{group___r_c_c_ex___exported___macros_ga1c11406787c87ef39597619fae00bd88} 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C123\+\_\+\+CONFIG}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_gafd775b802b35eddc3763819b696c8dc6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1235\+\_\+\+CONFIG}}
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga18d44d4471dc6940cdfa9ee4ad4025d3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C1235\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em macro to get the I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock source. \end{DoxyCompactList}\item 
\Hypertarget{group___r_c_c_ex___exported___macros_ga702d7cc3defaf9a4e69ab5ec4a262436}\label{group___r_c_c_ex___exported___macros_ga702d7cc3defaf9a4e69ab5ec4a262436} 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C123\+\_\+\+SOURCE}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga18d44d4471dc6940cdfa9ee4ad4025d3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C1235\+\_\+\+SOURCE}}
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga7cd89ab045ec9b7d5bda7da3e1587828}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+CONFIG}}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C123\+\_\+\+CONFIG
\begin{DoxyCompactList}\small\item\em macro to configure the I2\+C1 clock (I2\+C1\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gabc9e99366b5dfab7a6c535f8f48af8d3}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C1\+\_\+\+SOURCE}}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C123\+\_\+\+SOURCE
\begin{DoxyCompactList}\small\item\em macro to get the I2\+C1 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga96d9bad1e46c94af8387ca6dbfeea357}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+CONFIG}}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C123\+\_\+\+CONFIG
\begin{DoxyCompactList}\small\item\em macro to configure the I2\+C2 clock (I2\+C2\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gabaa32df2434beb7a446be4aba5c2a06b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C2\+\_\+\+SOURCE}}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C123\+\_\+\+SOURCE
\begin{DoxyCompactList}\small\item\em macro to get the I2\+C2 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga335a0313bb3a188435b39a11cf7c3eee}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+CONFIG}}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C123\+\_\+\+CONFIG
\begin{DoxyCompactList}\small\item\em macro to configure the I2\+C3 clock (I2\+C3\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga06f70ebfa24caeb198001d5c02d6dc78}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C3\+\_\+\+SOURCE}}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C123\+\_\+\+SOURCE
\begin{DoxyCompactList}\small\item\em macro to get the I2\+C3 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gac63fbd88afa59e3453a7d5d7c32fb1dc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C4\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+I2\+C4\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em macro to configure the I2\+C4 clock (I2\+C4\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga6632a1fbc809f6f6dedde0d36cbaa3c9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C4\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em macro to get the I2\+C4 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga5d331d1d7b05a87debf939ff00d961d5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART16910\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+USART16910\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em macro to configure the USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock (USART16\+CLK). \end{DoxyCompactList}\item 
\Hypertarget{group___r_c_c_ex___exported___macros_gacc82f34fbb358dd2cad032a06eaf7ede}\label{group___r_c_c_ex___exported___macros_gacc82f34fbb358dd2cad032a06eaf7ede} 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART16\+\_\+\+CONFIG}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga5d331d1d7b05a87debf939ff00d961d5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART16910\+\_\+\+CONFIG}}
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga4f9d49aa3d088259c585f7509736818c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART16910\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em macro to get the USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock source. \end{DoxyCompactList}\item 
\Hypertarget{group___r_c_c_ex___exported___macros_gad51ff313be41917e24d3b074f56bb0ba}\label{group___r_c_c_ex___exported___macros_gad51ff313be41917e24d3b074f56bb0ba} 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART16\+\_\+\+SOURCE}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga4f9d49aa3d088259c585f7509736818c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART16910\+\_\+\+SOURCE}}
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+USART234578\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em macro to configure the USART234578 clock (USART234578\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em macro to get the USART2/3/4/5/7/8 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga5c9ff3bd1509df21975b5a86202efd52}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+CONFIG}}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART16\+\_\+\+CONFIG
\begin{DoxyCompactList}\small\item\em macro to configure the USART1 clock (USART1\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga241bae96ad4a1ba687b3bf692e04f444}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART1\+\_\+\+SOURCE}}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART16\+\_\+\+SOURCE
\begin{DoxyCompactList}\small\item\em macro to get the USART1 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gaba22cefcb74b384a2e2fb3d2c51fae54}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+CONFIG}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}
\begin{DoxyCompactList}\small\item\em macro to configure the USART2 clock (USART2\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga59a86a292df891a219d5d4a8e26a45e9}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART2\+\_\+\+SOURCE}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}
\begin{DoxyCompactList}\small\item\em macro to get the USART2 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gac1a20f806bcd2ec6cc781bab1d99e5b5}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+CONFIG}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}
\begin{DoxyCompactList}\small\item\em macro to configure the USART3 clock (USART3\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga04818c61b18e167ea60f290ab52247db}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART3\+\_\+\+SOURCE}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}
\begin{DoxyCompactList}\small\item\em macro to get the USART3 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga711b187525b8b788b9f0ca968b1bd648}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CONFIG}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}
\begin{DoxyCompactList}\small\item\em macro to configure the UART4 clock (UART4\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga9945c36dd4ffce9d8c1b213e56edf80a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+UART4\+\_\+\+SOURCE}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}
\begin{DoxyCompactList}\small\item\em macro to get the UART4 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gae6c043e0b4091279d4db065b38b801b1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CONFIG}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}
\begin{DoxyCompactList}\small\item\em macro to configure the UART5 clock (UART5\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2c68fe07259568cba46c14fc4259933d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+UART5\+\_\+\+SOURCE}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}
\begin{DoxyCompactList}\small\item\em macro to get the UART5 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga28d9b1a1ce7ec3639b1d02ca10104704}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+CONFIG}}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART16\+\_\+\+CONFIG
\begin{DoxyCompactList}\small\item\em macro to configure the USART6 clock (USART6\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga134c539c1f80f684ee9722f08e4c89ea}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART6\+\_\+\+SOURCE}}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART16\+\_\+\+SOURCE
\begin{DoxyCompactList}\small\item\em macro to get the USART6 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga60bd7f1550266967e3f87a85afbddb7a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+CONFIG}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}
\begin{DoxyCompactList}\small\item\em macro to configure the UART5 clock (UART7\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga680abf193deaeff90542affda7d160d4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+UART7\+\_\+\+SOURCE}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}
\begin{DoxyCompactList}\small\item\em macro to get the UART7 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga492a06425e99e15b064d5278cf319722}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+CONFIG}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}
\begin{DoxyCompactList}\small\item\em macro to configure the UART8 clock (UART8\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga56b15263e2d6dcc75b362d96bf2f7397}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+UART8\+\_\+\+SOURCE}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}
\begin{DoxyCompactList}\small\item\em macro to get the UART8 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2859926bab56d03f5d4bfbf0941a0a3f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+LPUART1\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em macro to configure the LPUART1 clock (LPUART1\+CLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga193015f4df5fb541bd4fbbc20d1e20ae}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+LPUART1\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em macro to get the LPUART1 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga3ef78c8916149398bba06596863734ab}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+LPTIM1\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em macro to configure the LPTIM1 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gad6688c07a2a8c314df547de8caf378bb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+LPTIM1\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em macro to get the LPTIM1 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gabe82d482e8127576b6ce1f331fcc7e1a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+LPTIM2\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em macro to configure the LPTIM2 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga806f1d6e6a7d741b4d0524aa849f8ed8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+LPTIM2\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em macro to get the LPTIM2 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gac11efaec3a89a1b6d9696eb6e9e8048e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM345\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+LPTIM345\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em macro to configure the LPTIM3/4/5 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga6b2263ea1e054aee45c85e64dcfeb99f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+LPTIM345\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em macro to get the LPTIM3/4/5 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga36174050acd330e879a5d12bdbfb19c4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM3\+\_\+\+CONFIG}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_gac11efaec3a89a1b6d9696eb6e9e8048e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM345\+\_\+\+CONFIG}}
\begin{DoxyCompactList}\small\item\em macro to configure the LPTIM3 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga08d9d85cee6e2656f7a7b0cf920326b8}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+LPTIM3\+\_\+\+SOURCE}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga6b2263ea1e054aee45c85e64dcfeb99f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+LPTIM345\+\_\+\+SOURCE}}
\begin{DoxyCompactList}\small\item\em macro to get the LPTIM3 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga18a22f0e5f811ba9fee8bb2906dfa60b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+FMCCLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em macro to configure the FMC clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga48733b3d8faeb67777184a503bbbf2fa}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+FMC\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em macro to get the FMC clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga1c690ec86648d92efb97d2598a0cb2f1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+USBCLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the USB clock (USBCLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2b796e523b7f4c4cd7b5f06b7f995315}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USB\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the USB clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga03642b548896f327c3efc876aff4b349}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+ADCCLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the ADC clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2ee9f1838a8450f949b548a06ed3bc58}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+ADC\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the ADC clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gac23e7b662783a7131e3e892ff0c21f06}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+SWPMI1\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the SWPMI1 clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga3ddf343654e802758b5e779d81122404}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SWPMI1\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the SWPMI1 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga79c4e732154d11fb10e6b5752ab31fc4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+DFSDM1\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the DFSDM1 clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga5bd849cb75a56ae9a27a164e7d3c8575}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+DFSDM1\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the DFSDM1 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga7aff87df867beb2eb7eddbbfe06fcdc6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+CECCLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em macro to configure the CEC clock (CECCLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga7a636a5c50887bba7270924c3eb6ef2f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+CEC\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em macro to get the CEC clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gaa463f3972818967005d31114221e1cdc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CLKP\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+CLKPSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the CLKP \+: Oscillator clock for peripheral. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga5d047265ca753e28b45b09e53c3f50fe}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+CLKP\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the Oscillator clock for peripheral source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga8da215b69bc3712d5bb359c66198d374}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI123\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RCC\+\_\+\+SPI123\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to Configure the SPI1/2/3 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga28d7eae98ab899dc6e1d4e80b8aea33d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI123\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the SPI1/2/3 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga9b531a40f565975ef8901b48afddf1cc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+CONFIG}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga8da215b69bc3712d5bb359c66198d374}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI123\+\_\+\+CONFIG}}
\begin{DoxyCompactList}\small\item\em Macro to Configure the SPI1 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gaa390c5d70fdb5e8c4d9171a79e3e95a1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI1\+\_\+\+SOURCE}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga28d7eae98ab899dc6e1d4e80b8aea33d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI123\+\_\+\+SOURCE}}
\begin{DoxyCompactList}\small\item\em Macro to get the SPI1 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga03aafcdc3a862d9f10a5d1fcce4b549e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+CONFIG}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga8da215b69bc3712d5bb359c66198d374}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI123\+\_\+\+CONFIG}}
\begin{DoxyCompactList}\small\item\em Macro to Configure the SPI2 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gaf1fd8060d50a3ca2ee9e6d193546126e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI2\+\_\+\+SOURCE}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga28d7eae98ab899dc6e1d4e80b8aea33d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI123\+\_\+\+SOURCE}}
\begin{DoxyCompactList}\small\item\em Macro to get the SPI2 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga72e45b0673f5829c390032f8bbb24f17}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+CONFIG}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga8da215b69bc3712d5bb359c66198d374}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI123\+\_\+\+CONFIG}}
\begin{DoxyCompactList}\small\item\em Macro to Configure the SPI3 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga05c66c28f3d72c123bb284e106a0d99b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI3\+\_\+\+SOURCE}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga28d7eae98ab899dc6e1d4e80b8aea33d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI123\+\_\+\+SOURCE}}
\begin{DoxyCompactList}\small\item\em Macro to get the SPI3 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gaecfe51f0d81f0130e1a5a06408320b72}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI45\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RCC\+\_\+\+SPI45\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to Configure the SPI4/5 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gafdcff08fc3544c712d1f4d2d17994842}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI45\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the SPI4/5 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga04806afde06b2bc3b4e409b81fce5c41}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+CONFIG}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_gaecfe51f0d81f0130e1a5a06408320b72}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI45\+\_\+\+CONFIG}}
\begin{DoxyCompactList}\small\item\em Macro to Configure the SPI4 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gaffce7a01f11a975120059a0a2a322d01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI4\+\_\+\+SOURCE}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_gafdcff08fc3544c712d1f4d2d17994842}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI45\+\_\+\+SOURCE}}
\begin{DoxyCompactList}\small\item\em Macro to get the SPI4 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga14c138363b18bdee29cbb3ec82594b92}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+CONFIG}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_gaecfe51f0d81f0130e1a5a06408320b72}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI45\+\_\+\+CONFIG}}
\begin{DoxyCompactList}\small\item\em Macro to Configure the SPI5 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga8ad4e833262fabd7960aab8946928a5f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI5\+\_\+\+SOURCE}}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_gafdcff08fc3544c712d1f4d2d17994842}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI45\+\_\+\+SOURCE}}
\begin{DoxyCompactList}\small\item\em Macro to get the SPI5 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga1170019b0ed2e1301d2284c2af149f33}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RCC\+\_\+\+SPI6\+CLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to Configure the SPI6 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga8e7af9e242f90f474d245e72066e163f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI6\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the SPI6 clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga7754edd5cc00e691c5007f22d3a93d38}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+SDMMCCLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the SDMMC clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gacccdca63ee93770444eaab77cd831c75}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SDMMC\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em Macro to get the SDMMC clock. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gae34a5e47c3e3a519bfca1f4313a88f9f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+RNGCLKSource\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em macro to configure the RNG clock (RNGCLK). \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gad8f27c485f7252991877f8e423b73d46}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+RNG\+\_\+\+SOURCE}}()
\begin{DoxyCompactList}\small\item\em macro to get the RNG clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga292ca7c84f192778314125ed6d7c8333}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIMCLKPRESCALER}}(\+\_\+\+\_\+\+PRESC\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Macro to configure the Timers clocks prescalers. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gafca78bb6fbfed8a31ef7ee030d424b50}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT}}()
\begin{DoxyCompactList}\small\item\em Enable the RCC LSE CSS Extended Interrupt Line. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gaa5c2a31f367b8085be517e315b8c0196}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT}}()
\begin{DoxyCompactList}\small\item\em Disable the RCC LSE CSS Extended Interrupt Line. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gad5f8173d2752512c30375c9ca7890fbc}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+EVENT}}()
\begin{DoxyCompactList}\small\item\em Enable the RCC LSE CSS Event Line. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga20711e52b237c9c598c87d5329a9700f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+EVENT}}()
\begin{DoxyCompactList}\small\item\em Disable the RCC LSE CSS Event Line. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga45a0bf105427b24b377125346b2e597d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Enable the RCC LSE CSS Extended Interrupt Falling Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga5b8a28d3896b67495b996d001084885e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+FALLING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Disable the RCC LSE CSS Extended Interrupt Falling Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga14487ed9c109cb494cae4a9762b7c294}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Enable the RCC LSE CSS Extended Interrupt Rising Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2746b06cbf0f080a600f3f895c95f3fb}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+RISING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Disable the RCC LSE CSS Extended Interrupt Rising Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga075e9194bfc08b5da32af130a74e7cb4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Enable the RCC LSE CSS Extended Interrupt Rising \& Falling Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gacea34070069d535080039e3067aba82d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Disable the RCC LSE CSS Extended Interrupt Rising \& Falling Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga65fa248e1dd8c7258a50ba03c4e2ff85}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG}}()
\begin{DoxyCompactList}\small\item\em Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga6171e2da4b75a993142330025862864f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG}}()
\begin{DoxyCompactList}\small\item\em Clear the RCC LSE CSS EXTI flag. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gac5a7ed26daae142eb6cce551728ee88c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+GENERATE\+\_\+\+SWIT}}()
\begin{DoxyCompactList}\small\item\em Generate a Software interrupt on the RCC LSE CSS EXTI line. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gae7a58e5b7b665d6fdd5af5f444d8ca8a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+ENABLE\+\_\+\+IT}}(\+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Enable the specified CRS interrupts. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga83218d96e4d75af9508a18cb81ad1254}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+DISABLE\+\_\+\+IT}}(\+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Disable the specified CRS interrupts. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga86642491c37c596d1c07699030d40d48}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+GET\+\_\+\+IT\+\_\+\+SOURCE}}(\+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Check whether the CRS interrupt has occurred or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga4c5b57880a8c7e917998d0c6a73351fb}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+ERROR\+\_\+\+MASK}}~((uint32\+\_\+t)(\mbox{\hyperlink{group___r_c_c_ex___c_r_s___interrupt___sources_ga031f913312b8af1f38dc7c5adcd716f1}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+TRIMOVF}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___r_c_c_ex___c_r_s___interrupt___sources_gaf464654bbdfda5b86982fc4aa5b5a031}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCERR}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___r_c_c_ex___c_r_s___interrupt___sources_gac6b25a96e779b2f7ee3223101109ee33}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCMISS}}))
\begin{DoxyCompactList}\small\item\em Clear the CRS interrupt pending bits. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga8f7ada1acec652afe441dfc4515e18be}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CLEAR\+\_\+\+IT}}(\+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gad40507a114061cddd85528ecc7555e1b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+GET\+\_\+\+FLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Check whether the specified CRS flag is set or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga39626ad9573958c96dccc66d13b1b6fe}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+ERROR\+\_\+\+MASK}}~((uint32\+\_\+t)(\mbox{\hyperlink{group___r_c_c_ex___c_r_s___flags_ga4c4c324494f9c6469e53d225242c73d4}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+TRIMOVF}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___r_c_c_ex___c_r_s___flags_gad49f59e34225920835b69a34f1b4c02b}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCERR}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___r_c_c_ex___c_r_s___flags_ga78549e9f343ad843d6e5d45b4e08433c}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCMISS}}))
\begin{DoxyCompactList}\small\item\em Clear the CRS specified FLAG. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___exported___macros_gaf8b5160a2401847e5b9410c9a01e5922}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CLEAR\+\_\+\+FLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\end{DoxyCompactItemize}


\doxysubsubsubsection{Detailed Description}


\label{doc-define-members}
\Hypertarget{group___r_c_c_ex___exported___macros_doc-define-members}
\doxysubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___r_c_c_ex___exported___macros_ga03642b548896f327c3efc876aff4b349}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_ADC\_CONFIG@{\_\_HAL\_RCC\_ADC\_CONFIG}}
\index{\_\_HAL\_RCC\_ADC\_CONFIG@{\_\_HAL\_RCC\_ADC\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_ADC\_CONFIG}{\_\_HAL\_RCC\_ADC\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga03642b548896f327c3efc876aff4b349} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+ADCCLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_ADCSEL,\ (uint32\_t)(\_\_ADCCLKSource\_\_))}

\end{DoxyCode}


Macro to configure the ADC clock. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+ADCCLKSource\+\_\+\+\_\+} & specifies the ADC digital interface clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+ADCCLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+P Clock selected as ADC clock \item RCC\+\_\+\+ADCCLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+R Clock selected as ADC clock \item RCC\+\_\+\+ADCCLKSOURCE\+\_\+\+CLKP\+: CLKP Clock selected as ADC clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga7aff87df867beb2eb7eddbbfe06fcdc6}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_CEC\_CONFIG@{\_\_HAL\_RCC\_CEC\_CONFIG}}
\index{\_\_HAL\_RCC\_CEC\_CONFIG@{\_\_HAL\_RCC\_CEC\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_CEC\_CONFIG}{\_\_HAL\_RCC\_CEC\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga7aff87df867beb2eb7eddbbfe06fcdc6} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+CECCLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_CECSEL,\ (uint32\_t)(\_\_CECCLKSource\_\_))}

\end{DoxyCode}


macro to configure the CEC clock (CECCLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+CECCLKSource\+\_\+\+\_\+} & specifies the CEC clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+CECCLKSOURCE\+\_\+\+LSE\+: LSE selected as CEC clock \item RCC\+\_\+\+CECCLKSOURCE\+\_\+\+LSI\+: LSI selected as CEC clock \item RCC\+\_\+\+CECCLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as CEC clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_gaa463f3972818967005d31114221e1cdc}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_CLKP\_CONFIG@{\_\_HAL\_RCC\_CLKP\_CONFIG}}
\index{\_\_HAL\_RCC\_CLKP\_CONFIG@{\_\_HAL\_RCC\_CLKP\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_CLKP\_CONFIG}{\_\_HAL\_RCC\_CLKP\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gaa463f3972818967005d31114221e1cdc} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CLKP\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+CLKPSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_CKPERSEL,\ (uint32\_t)(\_\_CLKPSource\_\_))}

\end{DoxyCode}


Macro to configure the CLKP \+: Oscillator clock for peripheral. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+CLKPSource\+\_\+\+\_\+} & specifies Oscillator clock for peripheral This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+CLKPSOURCE\+\_\+\+HSI\+: HSI selected Oscillator clock for peripheral \item RCC\+\_\+\+CLKPSOURCE\+\_\+\+CSI\+: CSI selected Oscillator clock for peripheral \item RCC\+\_\+\+CLKPSOURCE\+\_\+\+HSE\+: HSE selected Oscillator clock for peripheral \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_gaf8b5160a2401847e5b9410c9a01e5922}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_CRS\_CLEAR\_FLAG@{\_\_HAL\_RCC\_CRS\_CLEAR\_FLAG}}
\index{\_\_HAL\_RCC\_CRS\_CLEAR\_FLAG@{\_\_HAL\_RCC\_CRS\_CLEAR\_FLAG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_CRS\_CLEAR\_FLAG}{\_\_HAL\_RCC\_CRS\_CLEAR\_FLAG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gaf8b5160a2401847e5b9410c9a01e5922} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CLEAR\+\_\+\+FLAG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{keywordflow}{do}\ \{\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ if(((\_\_FLAG\_\_)\ \&\ \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga39626ad9573958c96dccc66d13b1b6fe}{RCC\_CRS\_FLAG\_ERROR\_MASK}})\ !=\ 0U)\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ WRITE\_REG(CRS-\/>ICR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae67dc4a9e576468b0c322902c7c47793}{CRS\_ICR\_ERRC}}\ |\ ((\_\_FLAG\_\_)\ \&\ \string~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga39626ad9573958c96dccc66d13b1b6fe}{RCC\_CRS\_FLAG\_ERROR\_MASK}}));\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{keywordflow}{else}\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ WRITE\_REG(CRS-\/>ICR,\ (\_\_FLAG\_\_));\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}(0)}

\end{DoxyCode}
\Hypertarget{group___r_c_c_ex___exported___macros_ga8f7ada1acec652afe441dfc4515e18be}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_CRS\_CLEAR\_IT@{\_\_HAL\_RCC\_CRS\_CLEAR\_IT}}
\index{\_\_HAL\_RCC\_CRS\_CLEAR\_IT@{\_\_HAL\_RCC\_CRS\_CLEAR\_IT}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_CRS\_CLEAR\_IT}{\_\_HAL\_RCC\_CRS\_CLEAR\_IT}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga8f7ada1acec652afe441dfc4515e18be} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CLEAR\+\_\+\+IT(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{keywordflow}{do}\ \{\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ if(((\_\_INTERRUPT\_\_)\ \&\ \mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga4c5b57880a8c7e917998d0c6a73351fb}{RCC\_CRS\_IT\_ERROR\_MASK}})\ !=\ 0U)\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ WRITE\_REG(CRS-\/>ICR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae67dc4a9e576468b0c322902c7c47793}{CRS\_ICR\_ERRC}}\ |\ ((\_\_INTERRUPT\_\_)\ \&\ \string~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga4c5b57880a8c7e917998d0c6a73351fb}{RCC\_CRS\_IT\_ERROR\_MASK}}));\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{keywordflow}{else}\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ WRITE\_REG(CRS-\/>ICR,\ (\_\_INTERRUPT\_\_));\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}(0)}

\end{DoxyCode}
\Hypertarget{group___r_c_c_ex___exported___macros_ga83218d96e4d75af9508a18cb81ad1254}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_CRS\_DISABLE\_IT@{\_\_HAL\_RCC\_CRS\_DISABLE\_IT}}
\index{\_\_HAL\_RCC\_CRS\_DISABLE\_IT@{\_\_HAL\_RCC\_CRS\_DISABLE\_IT}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_CRS\_DISABLE\_IT}{\_\_HAL\_RCC\_CRS\_DISABLE\_IT}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga83218d96e4d75af9508a18cb81ad1254} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+DISABLE\+\_\+\+IT(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(CRS-\/>CR,\ (\_\_INTERRUPT\_\_))}

\end{DoxyCode}


Disable the specified CRS interrupts. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+} & specifies the CRS interrupt sources to be disabled. This parameter can be any combination of the following values\+: \begin{DoxyItemize}
\item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga772a7eb77eaea0622fb3e3b20275a37f}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCOK} SYNC event OK interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga8b9e2cbfa3fd8d7c18f81685c24a394f}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCWARN} SYNC warning interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga01a198f277ff33e6fd5a9c2a6ad908b9}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+ERR} Synchronization or trimming error interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_gadf2de3907d21dfaea6b2444d66adfe13}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+ESYNC} Expected SYNC interrupt \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gae7a58e5b7b665d6fdd5af5f444d8ca8a}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_CRS\_ENABLE\_IT@{\_\_HAL\_RCC\_CRS\_ENABLE\_IT}}
\index{\_\_HAL\_RCC\_CRS\_ENABLE\_IT@{\_\_HAL\_RCC\_CRS\_ENABLE\_IT}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_CRS\_ENABLE\_IT}{\_\_HAL\_RCC\_CRS\_ENABLE\_IT}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gae7a58e5b7b665d6fdd5af5f444d8ca8a} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+ENABLE\+\_\+\+IT(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(CRS-\/>CR,\ (\_\_INTERRUPT\_\_))}

\end{DoxyCode}


Enable the specified CRS interrupts. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+} & specifies the CRS interrupt sources to be enabled. This parameter can be any combination of the following values\+: \begin{DoxyItemize}
\item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga772a7eb77eaea0622fb3e3b20275a37f}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCOK} SYNC event OK interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga8b9e2cbfa3fd8d7c18f81685c24a394f}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCWARN} SYNC warning interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga01a198f277ff33e6fd5a9c2a6ad908b9}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+ERR} Synchronization or trimming error interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_gadf2de3907d21dfaea6b2444d66adfe13}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+ESYNC} Expected SYNC interrupt \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gad40507a114061cddd85528ecc7555e1b}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_CRS\_GET\_FLAG@{\_\_HAL\_RCC\_CRS\_GET\_FLAG}}
\index{\_\_HAL\_RCC\_CRS\_GET\_FLAG@{\_\_HAL\_RCC\_CRS\_GET\_FLAG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_CRS\_GET\_FLAG}{\_\_HAL\_RCC\_CRS\_GET\_FLAG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gad40507a114061cddd85528ecc7555e1b} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+GET\+\_\+\+FLAG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{(READ\_BIT(CRS-\/>ISR,\ (\_\_FLAG\_\_))\ ==\ (\_\_FLAG\_\_))}

\end{DoxyCode}


Check whether the specified CRS flag is set or not. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+FLAG\+\_\+\+\_\+} & specifies the flag to check. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item \doxylink{group___r_c_c_ex___c_r_s___flags_ga27e1ae14c7854ca42faf5379bea5ac39}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCOK} SYNC event OK \item \doxylink{group___r_c_c_ex___c_r_s___flags_ga244c3ca47b8099a79212ab10d8e823c9}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCWARN} SYNC warning \item \doxylink{group___r_c_c_ex___c_r_s___flags_ga92be7705ece62c427a262355305527fa}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+ERR} Error \item \doxylink{group___r_c_c_ex___c_r_s___flags_ga10697d7c12b710c52c26db522c11986b}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+ESYNC} Expected SYNC \item \doxylink{group___r_c_c_ex___c_r_s___flags_ga4c4c324494f9c6469e53d225242c73d4}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+TRIMOVF} Trimming overflow or underflow \item \doxylink{group___r_c_c_ex___c_r_s___flags_gad49f59e34225920835b69a34f1b4c02b}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCERR} SYNC error \item \doxylink{group___r_c_c_ex___c_r_s___flags_ga78549e9f343ad843d6e5d45b4e08433c}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCMISS} SYNC missed \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em The} & new state of {\itshape FLAG} (TRUE or FALSE). \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga86642491c37c596d1c07699030d40d48}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_CRS\_GET\_IT\_SOURCE@{\_\_HAL\_RCC\_CRS\_GET\_IT\_SOURCE}}
\index{\_\_HAL\_RCC\_CRS\_GET\_IT\_SOURCE@{\_\_HAL\_RCC\_CRS\_GET\_IT\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_CRS\_GET\_IT\_SOURCE}{\_\_HAL\_RCC\_CRS\_GET\_IT\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga86642491c37c596d1c07699030d40d48} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+GET\+\_\+\+IT\+\_\+\+SOURCE(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((READ\_BIT(CRS-\/>CR,\ (\_\_INTERRUPT\_\_))\ !=\ 0U)\ ?\ SET\ :\ RESET)}

\end{DoxyCode}


Check whether the CRS interrupt has occurred or not. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+} & specifies the CRS interrupt source to check. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga772a7eb77eaea0622fb3e3b20275a37f}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCOK} SYNC event OK interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga8b9e2cbfa3fd8d7c18f81685c24a394f}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCWARN} SYNC warning interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga01a198f277ff33e6fd5a9c2a6ad908b9}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+ERR} Synchronization or trimming error interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_gadf2de3907d21dfaea6b2444d66adfe13}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+ESYNC} Expected SYNC interrupt \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em The} & new state of {\bfseries{INTERRUPT}} (SET or RESET). \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga79c4e732154d11fb10e6b5752ab31fc4}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_DFSDM1\_CONFIG@{\_\_HAL\_RCC\_DFSDM1\_CONFIG}}
\index{\_\_HAL\_RCC\_DFSDM1\_CONFIG@{\_\_HAL\_RCC\_DFSDM1\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_DFSDM1\_CONFIG}{\_\_HAL\_RCC\_DFSDM1\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga79c4e732154d11fb10e6b5752ab31fc4} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+DFSDM1\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_DFSDM1SEL,\ (uint32\_t)(\_\_DFSDM1CLKSource\_\_))}

\end{DoxyCode}


Macro to configure the DFSDM1 clock. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+DFSDM1\+CLKSource\+\_\+\+\_\+} & specifies the DFSDM1 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+DFSDM1\+CLKSOURCE\+\_\+\+D2\+PCLK\+: D2\+PCLK Clock selected as DFSDM1 clock \item RCC\+\_\+\+DFSDM1\+CLKSOURCE\+\_\+\+SYS\+: System Clock selected as DFSDM1 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga18a22f0e5f811ba9fee8bb2906dfa60b}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_FMC\_CONFIG@{\_\_HAL\_RCC\_FMC\_CONFIG}}
\index{\_\_HAL\_RCC\_FMC\_CONFIG@{\_\_HAL\_RCC\_FMC\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_FMC\_CONFIG}{\_\_HAL\_RCC\_FMC\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga18a22f0e5f811ba9fee8bb2906dfa60b} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+FMCCLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_FMCSEL,\ (uint32\_t)(\_\_FMCCLKSource\_\_))}

\end{DoxyCode}


macro to configure the FMC clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+FMCCLKSource\+\_\+\+\_\+} & specifies the FMC clock source. \begin{DoxyItemize}
\item RCC\+\_\+\+RCC\+\_\+\+FMCCLKSOURCE\+\_\+\+D1\+HCLK\+: Domain1 HCLK Clock selected as FMC clock \item RCC\+\_\+\+RCC\+\_\+\+FMCCLKSOURCE\+\_\+\+PLL \+: PLL1\+\_\+Q Clock selected as FMC clock \item RCC\+\_\+\+RCC\+\_\+\+FMCCLKSOURCE\+\_\+\+PLL2 \+: PLL2\+\_\+R Clock selected as FMC clock \item RCC\+\_\+\+RCC\+\_\+\+FMCCLKSOURCE\+\_\+\+CLKP CLKP selected as FMC clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga2ee9f1838a8450f949b548a06ed3bc58}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_ADC\_SOURCE@{\_\_HAL\_RCC\_GET\_ADC\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_ADC\_SOURCE@{\_\_HAL\_RCC\_GET\_ADC\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_ADC\_SOURCE}{\_\_HAL\_RCC\_GET\_ADC\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga2ee9f1838a8450f949b548a06ed3bc58} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+ADC\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_ADCSEL)))}

\end{DoxyCode}


Macro to get the ADC clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+ADCCLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+P Clock selected as ADC clock \item RCC\+\_\+\+ADCCLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+R Clock selected as ADC clock \item RCC\+\_\+\+ADCCLKSOURCE\+\_\+\+CLKP\+: CLKP Clock selected as ADC clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga7a636a5c50887bba7270924c3eb6ef2f}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_CEC\_SOURCE@{\_\_HAL\_RCC\_GET\_CEC\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_CEC\_SOURCE@{\_\_HAL\_RCC\_GET\_CEC\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_CEC\_SOURCE}{\_\_HAL\_RCC\_GET\_CEC\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga7a636a5c50887bba7270924c3eb6ef2f} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+CEC\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_CECSEL)))}

\end{DoxyCode}


macro to get the CEC clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+CECCLKSOURCE\+\_\+\+LSE\+: LSE selected as CEC clock \item RCC\+\_\+\+CECCLKSOURCE\+\_\+\+LSI\+: LSI selected as CEC clock \item RCC\+\_\+\+CECCLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as CEC clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga5d047265ca753e28b45b09e53c3f50fe}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_CLKP\_SOURCE@{\_\_HAL\_RCC\_GET\_CLKP\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_CLKP\_SOURCE@{\_\_HAL\_RCC\_GET\_CLKP\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_CLKP\_SOURCE}{\_\_HAL\_RCC\_GET\_CLKP\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga5d047265ca753e28b45b09e53c3f50fe} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+CLKP\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_CKPERSEL)))}

\end{DoxyCode}


Macro to get the Oscillator clock for peripheral source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+CLKPSOURCE\+\_\+\+HSI\+: HSI selected Oscillator clock for peripheral \item RCC\+\_\+\+CLKPSOURCE\+\_\+\+CSI\+: CSI selected Oscillator clock for peripheral \item RCC\+\_\+\+CLKPSOURCE\+\_\+\+HSE\+: HSE selected Oscillator clock for peripheral \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga5bd849cb75a56ae9a27a164e7d3c8575}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_DFSDM1\_SOURCE@{\_\_HAL\_RCC\_GET\_DFSDM1\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_DFSDM1\_SOURCE@{\_\_HAL\_RCC\_GET\_DFSDM1\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_DFSDM1\_SOURCE}{\_\_HAL\_RCC\_GET\_DFSDM1\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga5bd849cb75a56ae9a27a164e7d3c8575} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+DFSDM1\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_DFSDM1SEL)))}

\end{DoxyCode}


Macro to get the DFSDM1 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+DFSDM1\+CLKSOURCE\+\_\+\+D2\+PCLK\+: D2\+PCLK Clock selected as DFSDM1 clock \item RCC\+\_\+\+DFSDM1\+CLKSOURCE\+\_\+\+SYS\+: System Clock selected as DFSDM1 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga48733b3d8faeb67777184a503bbbf2fa}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_FMC\_SOURCE@{\_\_HAL\_RCC\_GET\_FMC\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_FMC\_SOURCE@{\_\_HAL\_RCC\_GET\_FMC\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_FMC\_SOURCE}{\_\_HAL\_RCC\_GET\_FMC\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga48733b3d8faeb67777184a503bbbf2fa} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+FMC\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_FMCSEL)))}

\end{DoxyCode}


macro to get the FMC clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+RCC\+\_\+\+FMCCLKSOURCE\+\_\+\+D1\+HCLK\+: Domain1 HCLK Clock selected as FMC clock \item RCC\+\_\+\+RCC\+\_\+\+FMCCLKSOURCE\+\_\+\+PLL \+: PLL1\+\_\+Q Clock selected as FMC clock \item RCC\+\_\+\+RCC\+\_\+\+FMCCLKSOURCE\+\_\+\+PLL2 \+: PLL2\+\_\+R Clock selected as FMC clock \item RCC\+\_\+\+RCC\+\_\+\+FMCCLKSOURCE\+\_\+\+CLKP CLKP selected as FMC clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga18d44d4471dc6940cdfa9ee4ad4025d3}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_I2C1235\_SOURCE@{\_\_HAL\_RCC\_GET\_I2C1235\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_I2C1235\_SOURCE@{\_\_HAL\_RCC\_GET\_I2C1235\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_I2C1235\_SOURCE}{\_\_HAL\_RCC\_GET\_I2C1235\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga18d44d4471dc6940cdfa9ee4ad4025d3} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C1235\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>D2CCIP2R,\ RCC\_D2CCIP2R\_I2C1235SEL)))}

\end{DoxyCode}


macro to get the I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: D2\+PCLK1 selected as I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+PLL3\+: PLL3 selected as I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+CSI\+: CSI selected as I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock\end{DoxyItemize}
(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*})\+: Available on stm32h72xxx and stm32h73xxx family lines. \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gabc9e99366b5dfab7a6c535f8f48af8d3}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_I2C1\_SOURCE@{\_\_HAL\_RCC\_GET\_I2C1\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_I2C1\_SOURCE@{\_\_HAL\_RCC\_GET\_I2C1\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_I2C1\_SOURCE}{\_\_HAL\_RCC\_GET\_I2C1\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gabc9e99366b5dfab7a6c535f8f48af8d3} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C1\+\_\+\+SOURCE~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C123\+\_\+\+SOURCE}



macro to get the I2\+C1 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+I2\+C1\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: D2\+PCLK1 selected as I2\+C1 clock \item RCC\+\_\+\+I2\+C1\+CLKSOURCE\+\_\+\+PLL3\+: PLL3 selected as I2\+C1 clock \item RCC\+\_\+\+I2\+C1\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as I2\+C1 clock \item RCC\+\_\+\+I2\+C1\+CLKSOURCE\+\_\+\+CSI\+: CSI selected as I2\+C1 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gabaa32df2434beb7a446be4aba5c2a06b}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_I2C2\_SOURCE@{\_\_HAL\_RCC\_GET\_I2C2\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_I2C2\_SOURCE@{\_\_HAL\_RCC\_GET\_I2C2\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_I2C2\_SOURCE}{\_\_HAL\_RCC\_GET\_I2C2\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gabaa32df2434beb7a446be4aba5c2a06b} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C2\+\_\+\+SOURCE~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C123\+\_\+\+SOURCE}



macro to get the I2\+C2 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+I2\+C2\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: D2\+PCLK1 selected as I2\+C2 clock \item RCC\+\_\+\+I2\+C2\+CLKSOURCE\+\_\+\+PLL3\+: PLL3 selected as I2\+C2 clock \item RCC\+\_\+\+I2\+C2\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as I2\+C2 clock \item RCC\+\_\+\+I2\+C2\+CLKSOURCE\+\_\+\+CSI\+: CSI selected as I2\+C2 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga06f70ebfa24caeb198001d5c02d6dc78}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_I2C3\_SOURCE@{\_\_HAL\_RCC\_GET\_I2C3\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_I2C3\_SOURCE@{\_\_HAL\_RCC\_GET\_I2C3\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_I2C3\_SOURCE}{\_\_HAL\_RCC\_GET\_I2C3\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga06f70ebfa24caeb198001d5c02d6dc78} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C3\+\_\+\+SOURCE~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C123\+\_\+\+SOURCE}



macro to get the I2\+C3 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+I2\+C3\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: D2\+PCLK1 selected as I2\+C3 clock \item RCC\+\_\+\+I2\+C3\+CLKSOURCE\+\_\+\+PLL3\+: PLL3 selected as I2\+C3 clock \item RCC\+\_\+\+I2\+C3\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as I2\+C3 clock \item RCC\+\_\+\+I2\+C3\+CLKSOURCE\+\_\+\+CSI\+: CSI selected as I2\+C3 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga6632a1fbc809f6f6dedde0d36cbaa3c9}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_I2C4\_SOURCE@{\_\_HAL\_RCC\_GET\_I2C4\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_I2C4\_SOURCE@{\_\_HAL\_RCC\_GET\_I2C4\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_I2C4\_SOURCE}{\_\_HAL\_RCC\_GET\_I2C4\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga6632a1fbc809f6f6dedde0d36cbaa3c9} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+I2\+C4\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_I2C4SEL)))}

\end{DoxyCode}


macro to get the I2\+C4 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+D3\+PCLK1\+: D3\+PCLK1 selected as I2\+C4 clock \item RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+PLL3\+: PLL3 selected as I2\+C4 clock \item RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as I2\+C4 clock \item RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+CSI\+: CSI selected as I2\+C4 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gad6688c07a2a8c314df547de8caf378bb}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_LPTIM1\_SOURCE@{\_\_HAL\_RCC\_GET\_LPTIM1\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_LPTIM1\_SOURCE@{\_\_HAL\_RCC\_GET\_LPTIM1\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_LPTIM1\_SOURCE}{\_\_HAL\_RCC\_GET\_LPTIM1\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gad6688c07a2a8c314df547de8caf378bb} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+LPTIM1\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_LPTIM1SEL)))}

\end{DoxyCode}


macro to get the LPTIM1 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as LPTIM1 clock \item RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+P Clock selected as LPTIM1 clock \item RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+R Clock selected as LPTIM1 clock \item RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as LPTIM1 clock \item RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+LSI\+: LSI Clock selected as LPTIM1 clock \item RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+CLKP\+: CLKP selected as LPTIM1 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga806f1d6e6a7d741b4d0524aa849f8ed8}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_LPTIM2\_SOURCE@{\_\_HAL\_RCC\_GET\_LPTIM2\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_LPTIM2\_SOURCE@{\_\_HAL\_RCC\_GET\_LPTIM2\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_LPTIM2\_SOURCE}{\_\_HAL\_RCC\_GET\_LPTIM2\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga806f1d6e6a7d741b4d0524aa849f8ed8} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+LPTIM2\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_LPTIM2SEL)))}

\end{DoxyCode}


macro to get the LPTIM2 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+D3\+PCLK1\+: APB4 Clock selected as LPTIM2 clock \item RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+P Clock selected as LPTIM2 clock \item RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+R Clock selected as LPTIM2 clock \item RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as LPTIM2 clock \item RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+LSI\+: LSI Clock selected as LPTIM2 clock \item RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+CLKP\+: CLKP selected as LPTIM2 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga6b2263ea1e054aee45c85e64dcfeb99f}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_LPTIM345\_SOURCE@{\_\_HAL\_RCC\_GET\_LPTIM345\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_LPTIM345\_SOURCE@{\_\_HAL\_RCC\_GET\_LPTIM345\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_LPTIM345\_SOURCE}{\_\_HAL\_RCC\_GET\_LPTIM345\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga6b2263ea1e054aee45c85e64dcfeb99f} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+LPTIM345\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_LPTIM3SEL)))}

\end{DoxyCode}


macro to get the LPTIM3/4/5 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+LPTIM345\+CLKSOURCE\+\_\+\+D3\+PCLK1\+: APB4 Clock selected as LPTIM3/4/5 clock \item RCC\+\_\+\+LPTIM345\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+P Clock selected as LPTIM3/4/5 clock \item RCC\+\_\+\+LPTIM345\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+R Clock selected as LPTIM3/4/5 clock \item RCC\+\_\+\+LPTIM345\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as LPTIM3/4/5 clock \item RCC\+\_\+\+LPTIM345\+CLKSOURCE\+\_\+\+LSI\+: LSI Clock selected as LPTIM3/4/5 clock \item RCC\+\_\+\+LPTIM345\+CLKSOURCE\+\_\+\+CLKP\+: CLKP selected as LPTIM3/4/5 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga08d9d85cee6e2656f7a7b0cf920326b8}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_LPTIM3\_SOURCE@{\_\_HAL\_RCC\_GET\_LPTIM3\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_LPTIM3\_SOURCE@{\_\_HAL\_RCC\_GET\_LPTIM3\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_LPTIM3\_SOURCE}{\_\_HAL\_RCC\_GET\_LPTIM3\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga08d9d85cee6e2656f7a7b0cf920326b8} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+LPTIM3\+\_\+\+SOURCE~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga6b2263ea1e054aee45c85e64dcfeb99f}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+LPTIM345\+\_\+\+SOURCE}}}



macro to get the LPTIM3 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+LPTIM3\+CLKSOURCE\+\_\+\+D3\+PCLK1\+: APB4 Clock selected as LPTIM3 clock \item RCC\+\_\+\+LPTIM3\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+P Clock selected as LPTIM3 clock \item RCC\+\_\+\+LPTIM3\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+R Clock selected as LPTIM3 clock \item RCC\+\_\+\+LPTIM3\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as LPTIM3 clock \item RCC\+\_\+\+LPTIM3\+CLKSOURCE\+\_\+\+LSI\+: LSI Clock selected as LPTIM3 clock \item RCC\+\_\+\+LPTIM3\+CLKSOURCE\+\_\+\+CLKP\+: CLKP selected as LPTIM3 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga193015f4df5fb541bd4fbbc20d1e20ae}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_LPUART1\_SOURCE@{\_\_HAL\_RCC\_GET\_LPUART1\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_LPUART1\_SOURCE@{\_\_HAL\_RCC\_GET\_LPUART1\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_LPUART1\_SOURCE}{\_\_HAL\_RCC\_GET\_LPUART1\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga193015f4df5fb541bd4fbbc20d1e20ae} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+LPUART1\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_LPUART1SEL)))}

\end{DoxyCode}


macro to get the LPUART1 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+LPUART1\+CLKSOURCE\+\_\+\+D3\+PCLK1\+: APB4 Clock selected as LPUART1 clock \item RCC\+\_\+\+LPUART1\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as LPUART1 clock \item RCC\+\_\+\+LPUART1\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as LPUART1 clock \item RCC\+\_\+\+LPUART1\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as LPUART1 clock \item RCC\+\_\+\+LPUART1\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as LPUART1 clock \item RCC\+\_\+\+LPUART1\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as LPUART1 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gad8f27c485f7252991877f8e423b73d46}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_RNG\_SOURCE@{\_\_HAL\_RCC\_GET\_RNG\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_RNG\_SOURCE@{\_\_HAL\_RCC\_GET\_RNG\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_RNG\_SOURCE}{\_\_HAL\_RCC\_GET\_RNG\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gad8f27c485f7252991877f8e423b73d46} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+RNG\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_RNGSEL)))}

\end{DoxyCode}


macro to get the RNG clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+RNGCLKSOURCE\+\_\+\+HSI48\+: HSI48 selected as RNG clock \item RCC\+\_\+\+RNGCLKSOURCE\+\_\+\+PLL\+: PLL1Q selected as RNG clock \item RCC\+\_\+\+RNGCLKSOURCE\+\_\+\+LSE\+: LSE selected as RNG clock \item RCC\+\_\+\+RNGCLKSOURCE\+\_\+\+LSI\+: LSI selected as RNG clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga9af45dae7c2f2f1c8848be68d7bded7e}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_SAI1\_SOURCE@{\_\_HAL\_RCC\_GET\_SAI1\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_SAI1\_SOURCE@{\_\_HAL\_RCC\_GET\_SAI1\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_SAI1\_SOURCE}{\_\_HAL\_RCC\_GET\_SAI1\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga9af45dae7c2f2f1c8848be68d7bded7e} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SAI1\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SAI1SEL)))}

\end{DoxyCode}


Macro to get the SAI1 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SAI1\+CLKSOURCE\+\_\+\+PLL\+: SAI1 clock = PLL \item RCC\+\_\+\+SAI1\+CLKSOURCE\+\_\+\+PLL2\+: SAI1 clock = PLL2 \item RCC\+\_\+\+SAI1\+CLKSOURCE\+\_\+\+PLL3\+: SAI1 clock = PLL3 \item RCC\+\_\+\+SAI1\+CLKSOURCE\+\_\+\+CLKP\+: SAI1 clock = CLKP \item RCC\+\_\+\+SAI1\+CLKSOURCE\+\_\+\+PIN\+: SAI1 clock = External Clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gacccdca63ee93770444eaab77cd831c75}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_SDMMC\_SOURCE@{\_\_HAL\_RCC\_GET\_SDMMC\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_SDMMC\_SOURCE@{\_\_HAL\_RCC\_GET\_SDMMC\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_SDMMC\_SOURCE}{\_\_HAL\_RCC\_GET\_SDMMC\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gacccdca63ee93770444eaab77cd831c75} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SDMMC\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_SDMMCSEL)))}

\end{DoxyCode}


Macro to get the SDMMC clock. 

\Hypertarget{group___r_c_c_ex___exported___macros_gad3ddc626288e3b401da0b8547f2ac0d3}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_SPDIFRX\_SOURCE@{\_\_HAL\_RCC\_GET\_SPDIFRX\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_SPDIFRX\_SOURCE@{\_\_HAL\_RCC\_GET\_SPDIFRX\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_SPDIFRX\_SOURCE}{\_\_HAL\_RCC\_GET\_SPDIFRX\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gad3ddc626288e3b401da0b8547f2ac0d3} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPDIFRX\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SPDIFSEL)))}

\end{DoxyCode}


Macro to get the SPDIFRX clock source. 


\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga28d7eae98ab899dc6e1d4e80b8aea33d}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_SPI123\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI123\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_SPI123\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI123\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_SPI123\_SOURCE}{\_\_HAL\_RCC\_GET\_SPI123\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga28d7eae98ab899dc6e1d4e80b8aea33d} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI123\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SPI123SEL)))}

\end{DoxyCode}


Macro to get the SPI1/2/3 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+PLL\+: SPI1/2/3 clock = PLL \item RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+PLL2\+: SPI1/2/3 clock = PLL2 \item RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+PLL3\+: SPI1/2/3 clock = PLL3 \item RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+CLKP\+: SPI1/2/3 clock = CLKP \item RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+PIN\+: SPI1/2/3 clock = External Clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gaa390c5d70fdb5e8c4d9171a79e3e95a1}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_SPI1\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI1\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_SPI1\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI1\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_SPI1\_SOURCE}{\_\_HAL\_RCC\_GET\_SPI1\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gaa390c5d70fdb5e8c4d9171a79e3e95a1} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI1\+\_\+\+SOURCE~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga28d7eae98ab899dc6e1d4e80b8aea33d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI123\+\_\+\+SOURCE}}}



Macro to get the SPI1 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI1\+CLKSOURCE\+\_\+\+PLL\+: SPI1 clock = PLL \item RCC\+\_\+\+SPI1\+CLKSOURCE\+\_\+\+PLL2\+: SPI1 clock = PLL2 \item RCC\+\_\+\+SPI1\+CLKSOURCE\+\_\+\+PLL3\+: SPI1 clock = PLL3 \item RCC\+\_\+\+SPI1\+CLKSOURCE\+\_\+\+CLKP\+: SPI1 clock = CLKP \item RCC\+\_\+\+SPI1\+CLKSOURCE\+\_\+\+PIN\+: SPI1 clock = External Clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gaf1fd8060d50a3ca2ee9e6d193546126e}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_SPI2\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI2\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_SPI2\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI2\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_SPI2\_SOURCE}{\_\_HAL\_RCC\_GET\_SPI2\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gaf1fd8060d50a3ca2ee9e6d193546126e} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI2\+\_\+\+SOURCE~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga28d7eae98ab899dc6e1d4e80b8aea33d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI123\+\_\+\+SOURCE}}}



Macro to get the SPI2 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+PLL\+: SPI2 clock = PLL \item RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+PLL2\+: SPI2 clock = PLL2 \item RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+PLL3\+: SPI2 clock = PLL3 \item RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+CLKP\+: SPI2 clock = CLKP \item RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+PIN\+: SPI2 clock = External Clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga05c66c28f3d72c123bb284e106a0d99b}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_SPI3\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI3\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_SPI3\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI3\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_SPI3\_SOURCE}{\_\_HAL\_RCC\_GET\_SPI3\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga05c66c28f3d72c123bb284e106a0d99b} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI3\+\_\+\+SOURCE~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga28d7eae98ab899dc6e1d4e80b8aea33d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI123\+\_\+\+SOURCE}}}



Macro to get the SPI3 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI3\+CLKSOURCE\+\_\+\+PLL\+: SPI3 clock = PLL \item RCC\+\_\+\+SPI3\+CLKSOURCE\+\_\+\+PLL2\+: SPI3 clock = PLL2 \item RCC\+\_\+\+SPI3\+CLKSOURCE\+\_\+\+PLL3\+: SPI3 clock = PLL3 \item RCC\+\_\+\+SPI3\+CLKSOURCE\+\_\+\+CLKP\+: SPI3 clock = CLKP \item RCC\+\_\+\+SPI3\+CLKSOURCE\+\_\+\+PIN\+: SPI3 clock = External Clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gafdcff08fc3544c712d1f4d2d17994842}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_SPI45\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI45\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_SPI45\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI45\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_SPI45\_SOURCE}{\_\_HAL\_RCC\_GET\_SPI45\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gafdcff08fc3544c712d1f4d2d17994842} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI45\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SPI45SEL)))}

\end{DoxyCode}


Macro to get the SPI4/5 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI45\+CLKSOURCE\+\_\+\+D2\+PCLK2\+:SPI4/5 clock = D2\+PCLK2 \item RCC\+\_\+\+SPI45\+CLKSOURCE\+\_\+\+PLL2\+: SPI4/5 clock = PLL2 \item RCC\+\_\+\+SPI45\+CLKSOURCE\+\_\+\+PLL3\+: SPI4/5 clock = PLL3 \item RCC\+\_\+\+SPI45\+CLKSOURCE\+\_\+\+HSI\+: SPI4/5 clock = HSI \item RCC\+\_\+\+SPI45\+CLKSOURCE\+\_\+\+CSI\+: SPI4/5 clock = CSI \item RCC\+\_\+\+SPI45\+CLKSOURCE\+\_\+\+HSE\+: SPI4/5 clock = HSE \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gaffce7a01f11a975120059a0a2a322d01}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_SPI4\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI4\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_SPI4\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI4\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_SPI4\_SOURCE}{\_\_HAL\_RCC\_GET\_SPI4\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gaffce7a01f11a975120059a0a2a322d01} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI4\+\_\+\+SOURCE~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_gafdcff08fc3544c712d1f4d2d17994842}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI45\+\_\+\+SOURCE}}}



Macro to get the SPI4 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI4\+CLKSOURCE\+\_\+\+D2\+PCLK2\+:SPI4 clock = D2\+PCLK2 \item RCC\+\_\+\+SPI4\+CLKSOURCE\+\_\+\+PLL2\+: SPI4 clock = PLL2 \item RCC\+\_\+\+SPI4\+CLKSOURCE\+\_\+\+PLL3\+: SPI4 clock = PLL3 \item RCC\+\_\+\+SPI4\+CLKSOURCE\+\_\+\+HSI\+: SPI4 clock = HSI \item RCC\+\_\+\+SPI4\+CLKSOURCE\+\_\+\+CSI\+: SPI4 clock = CSI \item RCC\+\_\+\+SPI4\+CLKSOURCE\+\_\+\+HSE\+: SPI4 clock = HSE \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga8ad4e833262fabd7960aab8946928a5f}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_SPI5\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI5\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_SPI5\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI5\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_SPI5\_SOURCE}{\_\_HAL\_RCC\_GET\_SPI5\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga8ad4e833262fabd7960aab8946928a5f} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI5\+\_\+\+SOURCE~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_gafdcff08fc3544c712d1f4d2d17994842}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI45\+\_\+\+SOURCE}}}



Macro to get the SPI5 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI5\+CLKSOURCE\+\_\+\+D2\+PCLK2\+:SPI5 clock = D2\+PCLK2 \item RCC\+\_\+\+SPI5\+CLKSOURCE\+\_\+\+PLL2\+: SPI5 clock = PLL2 \item RCC\+\_\+\+SPI5\+CLKSOURCE\+\_\+\+PLL3\+: SPI5 clock = PLL3 \item RCC\+\_\+\+SPI5\+CLKSOURCE\+\_\+\+HSI\+: SPI5 clock = HSI \item RCC\+\_\+\+SPI5\+CLKSOURCE\+\_\+\+CSI\+: SPI5 clock = CSI \item RCC\+\_\+\+SPI5\+CLKSOURCE\+\_\+\+HSE\+: SPI5 clock = HSE \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga8e7af9e242f90f474d245e72066e163f}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_SPI6\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI6\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_SPI6\_SOURCE@{\_\_HAL\_RCC\_GET\_SPI6\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_SPI6\_SOURCE}{\_\_HAL\_RCC\_GET\_SPI6\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga8e7af9e242f90f474d245e72066e163f} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SPI6\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_SPI6SEL)))}

\end{DoxyCode}


Macro to get the SPI6 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+D3\+PCLK1\+:SPI6 clock = D2\+PCLK1 \item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+PLL2\+: SPI6 clock = PLL2 \item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+PLL3\+: SPI6 clock = PLL3 \item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+HSI\+: SPI6 clock = HSI \item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+CSI\+: SPI6 clock = CSI \item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+HSE\+: SPI6 clock = HSE \item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+PIN\+: SPI6 clock = I2\+S\+\_\+\+CKIN \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga3ddf343654e802758b5e779d81122404}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_SWPMI1\_SOURCE@{\_\_HAL\_RCC\_GET\_SWPMI1\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_SWPMI1\_SOURCE@{\_\_HAL\_RCC\_GET\_SWPMI1\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_SWPMI1\_SOURCE}{\_\_HAL\_RCC\_GET\_SWPMI1\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga3ddf343654e802758b5e779d81122404} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+SWPMI1\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SWPSEL)))}

\end{DoxyCode}


Macro to get the SWPMI1 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SWPMI1\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: D2\+PCLK1 Clock selected as SWPMI1 clock \item RCC\+\_\+\+SWPMI1\+CLKSOURCE\+\_\+\+HSI\+: HSI Clock selected as SWPMI1 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga9945c36dd4ffce9d8c1b213e56edf80a}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_UART4\_SOURCE@{\_\_HAL\_RCC\_GET\_UART4\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_UART4\_SOURCE@{\_\_HAL\_RCC\_GET\_UART4\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_UART4\_SOURCE}{\_\_HAL\_RCC\_GET\_UART4\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga9945c36dd4ffce9d8c1b213e56edf80a} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+UART4\+\_\+\+SOURCE~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}}



macro to get the UART4 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+UART4\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as UART4 clock \item RCC\+\_\+\+UART4\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as UART4 clock \item RCC\+\_\+\+UART4\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as UART4 clock \item RCC\+\_\+\+UART4\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as UART4 clock \item RCC\+\_\+\+UART4\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as UART4 clock \item RCC\+\_\+\+UART4\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as UART4 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga2c68fe07259568cba46c14fc4259933d}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_UART5\_SOURCE@{\_\_HAL\_RCC\_GET\_UART5\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_UART5\_SOURCE@{\_\_HAL\_RCC\_GET\_UART5\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_UART5\_SOURCE}{\_\_HAL\_RCC\_GET\_UART5\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga2c68fe07259568cba46c14fc4259933d} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+UART5\+\_\+\+SOURCE~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}}



macro to get the UART5 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+UART5\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as UART5 clock \item RCC\+\_\+\+UART5\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as UART5 clock \item RCC\+\_\+\+UART5\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as UART5 clock \item RCC\+\_\+\+UART5\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as UART5 clock \item RCC\+\_\+\+UART5\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as UART5 clock \item RCC\+\_\+\+UART5\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as UART5 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga680abf193deaeff90542affda7d160d4}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_UART7\_SOURCE@{\_\_HAL\_RCC\_GET\_UART7\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_UART7\_SOURCE@{\_\_HAL\_RCC\_GET\_UART7\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_UART7\_SOURCE}{\_\_HAL\_RCC\_GET\_UART7\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga680abf193deaeff90542affda7d160d4} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+UART7\+\_\+\+SOURCE~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}}



macro to get the UART7 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+UART7\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as UART7 clock \item RCC\+\_\+\+UART7\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as UART7 clock \item RCC\+\_\+\+UART7\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as UART7 clock \item RCC\+\_\+\+UART7\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as UART7 clock \item RCC\+\_\+\+UART7\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as UART7 clock \item RCC\+\_\+\+UART7\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as UART7 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga56b15263e2d6dcc75b362d96bf2f7397}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_UART8\_SOURCE@{\_\_HAL\_RCC\_GET\_UART8\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_UART8\_SOURCE@{\_\_HAL\_RCC\_GET\_UART8\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_UART8\_SOURCE}{\_\_HAL\_RCC\_GET\_UART8\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga56b15263e2d6dcc75b362d96bf2f7397} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+UART8\+\_\+\+SOURCE~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}}



macro to get the UART8 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+UART8\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as UART8 clock \item RCC\+\_\+\+UART8\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as UART8 clock \item RCC\+\_\+\+UART8\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as UART8 clock \item RCC\+\_\+\+UART8\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as UART8 clock \item RCC\+\_\+\+UART8\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as UART8 clock \item RCC\+\_\+\+UART8\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as UART8 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga4f9d49aa3d088259c585f7509736818c}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_USART16910\_SOURCE@{\_\_HAL\_RCC\_GET\_USART16910\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_USART16910\_SOURCE@{\_\_HAL\_RCC\_GET\_USART16910\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_USART16910\_SOURCE}{\_\_HAL\_RCC\_GET\_USART16910\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga4f9d49aa3d088259c585f7509736818c} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART16910\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>D2CCIP2R,\ RCC\_D2CCIP2R\_USART16910SEL)))}

\end{DoxyCode}


macro to get the USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USART16\+CLKSOURCE\+\_\+\+D2\+PCLK2\+: APB2 Clock selected as USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+USART16\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+USART16\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+USART16\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+USART16\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+USART16\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock\end{DoxyItemize}
(\texorpdfstring{$\ast$}{*}) \+: Available on some STM32\+H7 lines only. \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga241bae96ad4a1ba687b3bf692e04f444}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_USART1\_SOURCE@{\_\_HAL\_RCC\_GET\_USART1\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_USART1\_SOURCE@{\_\_HAL\_RCC\_GET\_USART1\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_USART1\_SOURCE}{\_\_HAL\_RCC\_GET\_USART1\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga241bae96ad4a1ba687b3bf692e04f444} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART1\+\_\+\+SOURCE~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART16\+\_\+\+SOURCE}



macro to get the USART1 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USART1\+CLKSOURCE\+\_\+\+D2\+PCLK2\+: APB2 Clock selected as USART1 clock \item RCC\+\_\+\+USART1\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as USART1 clock \item RCC\+\_\+\+USART1\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as USART1 clock \item RCC\+\_\+\+USART1\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as USART1 clock \item RCC\+\_\+\+USART1\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as USART1 clock \item RCC\+\_\+\+USART1\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as USART1 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_USART234578\_SOURCE@{\_\_HAL\_RCC\_GET\_USART234578\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_USART234578\_SOURCE@{\_\_HAL\_RCC\_GET\_USART234578\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_USART234578\_SOURCE}{\_\_HAL\_RCC\_GET\_USART234578\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_USART234578SEL)))}

\end{DoxyCode}


macro to get the USART2/3/4/5/7/8 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USART234578\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as USART2/3/4/5/7/8 clock \item RCC\+\_\+\+USART234578\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as USART2/3/4/5/7/8 clock \item RCC\+\_\+\+USART234578\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as USART2/3/4/5/7/8 clock \item RCC\+\_\+\+USART234578\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as USART2/3/4/5/7/8 clock \item RCC\+\_\+\+USART234578\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as USART2/3/4/5/7/8 clock \item RCC\+\_\+\+USART234578\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as USART2/3/4/5/7/8 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga59a86a292df891a219d5d4a8e26a45e9}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_USART2\_SOURCE@{\_\_HAL\_RCC\_GET\_USART2\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_USART2\_SOURCE@{\_\_HAL\_RCC\_GET\_USART2\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_USART2\_SOURCE}{\_\_HAL\_RCC\_GET\_USART2\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga59a86a292df891a219d5d4a8e26a45e9} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART2\+\_\+\+SOURCE~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}}



macro to get the USART2 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as USART2 clock \item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as USART2 clock \item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as USART2 clock \item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as USART2 clock \item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as USART2 clock \item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as USART2 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga04818c61b18e167ea60f290ab52247db}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_USART3\_SOURCE@{\_\_HAL\_RCC\_GET\_USART3\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_USART3\_SOURCE@{\_\_HAL\_RCC\_GET\_USART3\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_USART3\_SOURCE}{\_\_HAL\_RCC\_GET\_USART3\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga04818c61b18e167ea60f290ab52247db} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART3\+\_\+\+SOURCE~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga2de2c847f3e490a5b6ac8b1d13b66883}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART234578\+\_\+\+SOURCE}}}



macro to get the USART3 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as USART3 clock \item RCC\+\_\+\+USART3\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as USART3 clock \item RCC\+\_\+\+USART3\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as USART3 clock \item RCC\+\_\+\+USART3\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as USART3 clock \item RCC\+\_\+\+USART3\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as USART3 clock \item RCC\+\_\+\+USART3\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as USART3 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga134c539c1f80f684ee9722f08e4c89ea}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_USART6\_SOURCE@{\_\_HAL\_RCC\_GET\_USART6\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_USART6\_SOURCE@{\_\_HAL\_RCC\_GET\_USART6\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_USART6\_SOURCE}{\_\_HAL\_RCC\_GET\_USART6\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga134c539c1f80f684ee9722f08e4c89ea} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART6\+\_\+\+SOURCE~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USART16\+\_\+\+SOURCE}



macro to get the USART6 clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USART6\+CLKSOURCE\+\_\+\+D2\+PCLK2\+: APB2 Clock selected as USART6 clock \item RCC\+\_\+\+USART6\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as USART6 clock \item RCC\+\_\+\+USART6\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as USART6 clock \item RCC\+\_\+\+USART6\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as USART6 clock \item RCC\+\_\+\+USART6\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as USART6 clock \item RCC\+\_\+\+USART6\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as USART6 clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga2b796e523b7f4c4cd7b5f06b7f995315}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_GET\_USB\_SOURCE@{\_\_HAL\_RCC\_GET\_USB\_SOURCE}}
\index{\_\_HAL\_RCC\_GET\_USB\_SOURCE@{\_\_HAL\_RCC\_GET\_USB\_SOURCE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_GET\_USB\_SOURCE}{\_\_HAL\_RCC\_GET\_USB\_SOURCE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga2b796e523b7f4c4cd7b5f06b7f995315} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+USB\+\_\+\+SOURCE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{((uint32\_t)(READ\_BIT(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_USBSEL)))}

\end{DoxyCode}


Macro to get the USB clock source. 


\begin{DoxyRetVals}{Return values}
{\em The} & clock source can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USBCLKSOURCE\+\_\+\+PLL\+: PLL1Q selected as USB clock \item RCC\+\_\+\+USBCLKSOURCE\+\_\+\+PLL3\+: PLL3Q Clock selected as USB clock \item RCC\+\_\+\+USBCLKSOURCE\+\_\+\+HSI48\+: RC48 MHZ Clock selected as USB clock \end{DoxyItemize}
\\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gafd775b802b35eddc3763819b696c8dc6}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_I2C1235\_CONFIG@{\_\_HAL\_RCC\_I2C1235\_CONFIG}}
\index{\_\_HAL\_RCC\_I2C1235\_CONFIG@{\_\_HAL\_RCC\_I2C1235\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_I2C1235\_CONFIG}{\_\_HAL\_RCC\_I2C1235\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gafd775b802b35eddc3763819b696c8dc6} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1235\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+I2\+C1235\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>D2CCIP2R,\ RCC\_D2CCIP2R\_I2C1235SEL,\ (uint32\_t)(\_\_I2C1235CLKSource\_\_))}

\end{DoxyCode}


macro to configure the I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock (I2\+C123\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+I2\+C1235\+CLKSource\+\_\+\+\_\+} & specifies the I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: D2\+PCLK1 selected as I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+PLL3\+: PLL3 selected as I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+CSI\+: CSI selected as I2\+C1/2/3/5\texorpdfstring{$\ast$}{*} clock\end{DoxyItemize}
(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*})\+: Available on stm32h72xxx and stm32h73xxx family lines. \\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga7cd89ab045ec9b7d5bda7da3e1587828}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_I2C1\_CONFIG@{\_\_HAL\_RCC\_I2C1\_CONFIG}}
\index{\_\_HAL\_RCC\_I2C1\_CONFIG@{\_\_HAL\_RCC\_I2C1\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_I2C1\_CONFIG}{\_\_HAL\_RCC\_I2C1\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga7cd89ab045ec9b7d5bda7da3e1587828} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+CONFIG~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C123\+\_\+\+CONFIG}



macro to configure the I2\+C1 clock (I2\+C1\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+I2\+C1\+CLKSource\+\_\+\+\_\+} & specifies the I2\+C1 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+I2\+C1\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: D2\+PCLK1 selected as I2\+C1 clock \item RCC\+\_\+\+I2\+C1\+CLKSOURCE\+\_\+\+PLL3\+: PLL3 selected as I2\+C1 clock \item RCC\+\_\+\+I2\+C1\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as I2\+C1 clock \item RCC\+\_\+\+I2\+C1\+CLKSOURCE\+\_\+\+CSI\+: CSI selected as I2\+C1 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga96d9bad1e46c94af8387ca6dbfeea357}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_I2C2\_CONFIG@{\_\_HAL\_RCC\_I2C2\_CONFIG}}
\index{\_\_HAL\_RCC\_I2C2\_CONFIG@{\_\_HAL\_RCC\_I2C2\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_I2C2\_CONFIG}{\_\_HAL\_RCC\_I2C2\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga96d9bad1e46c94af8387ca6dbfeea357} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+CONFIG~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C123\+\_\+\+CONFIG}



macro to configure the I2\+C2 clock (I2\+C2\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+I2\+C2\+CLKSource\+\_\+\+\_\+} & specifies the I2\+C2 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+I2\+C2\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: D2\+PCLK1 selected as I2\+C2 clock \item RCC\+\_\+\+I2\+C2\+CLKSOURCE\+\_\+\+PLL3\+: PLL3 selected as I2\+C2 clock \item RCC\+\_\+\+I2\+C2\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as I2\+C2 clock \item RCC\+\_\+\+I2\+C2\+CLKSOURCE\+\_\+\+CSI\+: CSI selected as I2\+C2 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga335a0313bb3a188435b39a11cf7c3eee}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_I2C3\_CONFIG@{\_\_HAL\_RCC\_I2C3\_CONFIG}}
\index{\_\_HAL\_RCC\_I2C3\_CONFIG@{\_\_HAL\_RCC\_I2C3\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_I2C3\_CONFIG}{\_\_HAL\_RCC\_I2C3\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga335a0313bb3a188435b39a11cf7c3eee} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+CONFIG~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C123\+\_\+\+CONFIG}



macro to configure the I2\+C3 clock (I2\+C3\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+I2\+C3\+CLKSource\+\_\+\+\_\+} & specifies the I2\+C3 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+I2\+C3\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: D2\+PCLK1 selected as I2\+C3 clock \item RCC\+\_\+\+I2\+C3\+CLKSOURCE\+\_\+\+PLL3\+: PLL3 selected as I2\+C3 clock \item RCC\+\_\+\+I2\+C3\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as I2\+C3 clock \item RCC\+\_\+\+I2\+C3\+CLKSOURCE\+\_\+\+CSI\+: CSI selected as I2\+C3 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_gac63fbd88afa59e3453a7d5d7c32fb1dc}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_I2C4\_CONFIG@{\_\_HAL\_RCC\_I2C4\_CONFIG}}
\index{\_\_HAL\_RCC\_I2C4\_CONFIG@{\_\_HAL\_RCC\_I2C4\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_I2C4\_CONFIG}{\_\_HAL\_RCC\_I2C4\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gac63fbd88afa59e3453a7d5d7c32fb1dc} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C4\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+I2\+C4\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_I2C4SEL,\ (uint32\_t)(\_\_I2C4CLKSource\_\_))}

\end{DoxyCode}


macro to configure the I2\+C4 clock (I2\+C4\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+I2\+C4\+CLKSource\+\_\+\+\_\+} & specifies the I2\+C4 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+D3\+PCLK1\+: D3\+PCLK1 selected as I2\+C4 clock \item RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+PLL3\+: PLL3 selected as I2\+C4 clock \item RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as I2\+C4 clock \item RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+CSI\+: CSI selected as I2\+C4 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga3ef78c8916149398bba06596863734ab}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LPTIM1\_CONFIG@{\_\_HAL\_RCC\_LPTIM1\_CONFIG}}
\index{\_\_HAL\_RCC\_LPTIM1\_CONFIG@{\_\_HAL\_RCC\_LPTIM1\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LPTIM1\_CONFIG}{\_\_HAL\_RCC\_LPTIM1\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga3ef78c8916149398bba06596863734ab} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+LPTIM1\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_LPTIM1SEL,\ (uint32\_t)(\_\_LPTIM1CLKSource\_\_))}

\end{DoxyCode}


macro to configure the LPTIM1 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+LPTIM1\+CLKSource\+\_\+\+\_\+} & specifies the LPTIM1 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as LPTIM1 clock \item RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+P Clock selected as LPTIM1 clock \item RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+R Clock selected as LPTIM1 clock \item RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as LPTIM1 clock \item RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+LSI\+: LSI Clock selected as LPTIM1 clock \item RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+CLKP\+: CLKP selected as LPTIM1 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_gabe82d482e8127576b6ce1f331fcc7e1a}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LPTIM2\_CONFIG@{\_\_HAL\_RCC\_LPTIM2\_CONFIG}}
\index{\_\_HAL\_RCC\_LPTIM2\_CONFIG@{\_\_HAL\_RCC\_LPTIM2\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LPTIM2\_CONFIG}{\_\_HAL\_RCC\_LPTIM2\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gabe82d482e8127576b6ce1f331fcc7e1a} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+LPTIM2\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_LPTIM2SEL,\ (uint32\_t)(\_\_LPTIM2CLKSource\_\_))}

\end{DoxyCode}


macro to configure the LPTIM2 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+LPTIM2\+CLKSource\+\_\+\+\_\+} & specifies the LPTIM2 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+D3\+PCLK1\+: APB4 Clock selected as LPTIM2 clock \item RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+P Clock selected as LPTIM2 clock \item RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+R Clock selected as LPTIM2 clock \item RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as LPTIM2 clock \item RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+LSI\+: LSI Clock selected as LPTIM2 clock \item RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+CLKP\+: CLKP selected as LPTIM2 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_gac11efaec3a89a1b6d9696eb6e9e8048e}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LPTIM345\_CONFIG@{\_\_HAL\_RCC\_LPTIM345\_CONFIG}}
\index{\_\_HAL\_RCC\_LPTIM345\_CONFIG@{\_\_HAL\_RCC\_LPTIM345\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LPTIM345\_CONFIG}{\_\_HAL\_RCC\_LPTIM345\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gac11efaec3a89a1b6d9696eb6e9e8048e} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM345\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+LPTIM345\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_LPTIM3SEL,\ (uint32\_t)(\_\_LPTIM345CLKSource\_\_))}

\end{DoxyCode}


macro to configure the LPTIM3/4/5 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+LPTIM345\+CLKSource\+\_\+\+\_\+} & specifies the LPTIM3/4/5 clock source. \begin{DoxyItemize}
\item RCC\+\_\+\+LPTIM345\+CLKSOURCE\+\_\+\+D3\+PCLK1\+: APB4 Clock selected as LPTIM3/4/5 clock \item RCC\+\_\+\+LPTIM345\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+P Clock selected as LPTIM3/4/5 clock \item RCC\+\_\+\+LPTIM345\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+R Clock selected as LPTIM3/4/5 clock \item RCC\+\_\+\+LPTIM345\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as LPTIM3/4/5 clock \item RCC\+\_\+\+LPTIM345\+CLKSOURCE\+\_\+\+LSI\+: LSI Clock selected as LPTIM3/4/5 clock \item RCC\+\_\+\+LPTIM345\+CLKSOURCE\+\_\+\+CLKP\+: CLKP selected as LPTIM3/4/5 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga36174050acd330e879a5d12bdbfb19c4}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LPTIM3\_CONFIG@{\_\_HAL\_RCC\_LPTIM3\_CONFIG}}
\index{\_\_HAL\_RCC\_LPTIM3\_CONFIG@{\_\_HAL\_RCC\_LPTIM3\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LPTIM3\_CONFIG}{\_\_HAL\_RCC\_LPTIM3\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga36174050acd330e879a5d12bdbfb19c4} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM3\+\_\+\+CONFIG~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_gac11efaec3a89a1b6d9696eb6e9e8048e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM345\+\_\+\+CONFIG}}}



macro to configure the LPTIM3 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+LPTIM3\+CLKSource\+\_\+\+\_\+} & specifies the LPTIM3 clock source. \begin{DoxyItemize}
\item RCC\+\_\+\+LPTIM3\+CLKSOURCE\+\_\+\+D3\+PCLK1\+: APB4 Clock selected as LPTIM3 clock \item RCC\+\_\+\+LPTIM3\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+P Clock selected as LPTIM3 clock \item RCC\+\_\+\+LPTIM3\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+R Clock selected as LPTIM3 clock \item RCC\+\_\+\+LPTIM3\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as LPTIM3 clock \item RCC\+\_\+\+LPTIM3\+CLKSOURCE\+\_\+\+LSI\+: LSI Clock selected as LPTIM3 clock \item RCC\+\_\+\+LPTIM3\+CLKSOURCE\+\_\+\+CLKP\+: CLKP selected as LPTIM3 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga2859926bab56d03f5d4bfbf0941a0a3f}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LPUART1\_CONFIG@{\_\_HAL\_RCC\_LPUART1\_CONFIG}}
\index{\_\_HAL\_RCC\_LPUART1\_CONFIG@{\_\_HAL\_RCC\_LPUART1\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LPUART1\_CONFIG}{\_\_HAL\_RCC\_LPUART1\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga2859926bab56d03f5d4bfbf0941a0a3f} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+LPUART1\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_LPUART1SEL,\ (uint32\_t)(\_\_LPUART1CLKSource\_\_))}

\end{DoxyCode}


macro to configure the LPUART1 clock (LPUART1\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+LPUART1\+CLKSource\+\_\+\+\_\+} & specifies the LPUART1 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+LPUART1\+CLKSOURCE\+\_\+\+D3\+PCLK1\+: APB4 Clock selected as LPUART1 clock \item RCC\+\_\+\+LPUART1\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as LPUART1 clock \item RCC\+\_\+\+LPUART1\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as LPUART1 clock \item RCC\+\_\+\+LPUART1\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as LPUART1 clock \item RCC\+\_\+\+LPUART1\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as LPUART1 clock \item RCC\+\_\+\+LPUART1\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as LPUART1 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga6171e2da4b75a993142330025862864f}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_CLEAR\_FLAG@{\_\_HAL\_RCC\_LSECSS\_EXTI\_CLEAR\_FLAG}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_CLEAR\_FLAG@{\_\_HAL\_RCC\_LSECSS\_EXTI\_CLEAR\_FLAG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_CLEAR\_FLAG}{\_\_HAL\_RCC\_LSECSS\_EXTI\_CLEAR\_FLAG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga6171e2da4b75a993142330025862864f} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{WRITE\_REG(EXTI-\/>PR1,\ \mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_ga9b28da23df63fe2a235536edd669d8e9}{RCC\_EXTI\_LINE\_LSECSS}})}

\end{DoxyCode}


Clear the RCC LSE CSS EXTI flag. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga20711e52b237c9c598c87d5329a9700f}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_EVENT@{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_EVENT}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_EVENT@{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_EVENT}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_EVENT}{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_EVENT}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga20711e52b237c9c598c87d5329a9700f} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+EVENT(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(EXTI-\/>EMR1,\ \mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_ga9b28da23df63fe2a235536edd669d8e9}{RCC\_EXTI\_LINE\_LSECSS}})}

\end{DoxyCode}


Disable the RCC LSE CSS Event Line. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga5b8a28d3896b67495b996d001084885e}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_FALLING\_EDGE@{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_FALLING\_EDGE}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_FALLING\_EDGE@{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_FALLING\_EDGE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_FALLING\_EDGE}{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_FALLING\_EDGE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga5b8a28d3896b67495b996d001084885e} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+FALLING\+\_\+\+EDGE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(EXTI-\/>FTSR1,\ \mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_ga9b28da23df63fe2a235536edd669d8e9}{RCC\_EXTI\_LINE\_LSECSS}})}

\end{DoxyCode}


Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gaa5c2a31f367b8085be517e315b8c0196}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_IT@{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_IT}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_IT@{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_IT}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_IT}{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_IT}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gaa5c2a31f367b8085be517e315b8c0196} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(EXTI-\/>IMR1,\ \mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_ga9b28da23df63fe2a235536edd669d8e9}{RCC\_EXTI\_LINE\_LSECSS}})}

\end{DoxyCode}


Disable the RCC LSE CSS Extended Interrupt Line. 


\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga2746b06cbf0f080a600f3f895c95f3fb}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_EDGE@{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_EDGE}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_EDGE@{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_EDGE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_EDGE}{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_EDGE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga2746b06cbf0f080a600f3f895c95f3fb} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+RISING\+\_\+\+EDGE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(EXTI-\/>RTSR1,\ \mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_ga9b28da23df63fe2a235536edd669d8e9}{RCC\_EXTI\_LINE\_LSECSS}})}

\end{DoxyCode}


Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gacea34070069d535080039e3067aba82d}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_FALLING\_EDGE@{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_FALLING\_EDGE}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_FALLING\_EDGE@{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_FALLING\_EDGE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_FALLING\_EDGE}{\_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_FALLING\_EDGE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gacea34070069d535080039e3067aba82d} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \textcolor{keywordflow}{do}\ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_RISING\_EDGE();\ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \_\_HAL\_RCC\_LSECSS\_EXTI\_DISABLE\_FALLING\_EDGE();\ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \}\ \textcolor{keywordflow}{while}(0)}

\end{DoxyCode}


Disable the RCC LSE CSS Extended Interrupt Rising \& Falling Trigger. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gad5f8173d2752512c30375c9ca7890fbc}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_EVENT@{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_EVENT}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_EVENT@{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_EVENT}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_EVENT}{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_EVENT}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gad5f8173d2752512c30375c9ca7890fbc} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+EVENT(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(EXTI-\/>EMR1,\ \mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_ga9b28da23df63fe2a235536edd669d8e9}{RCC\_EXTI\_LINE\_LSECSS}})}

\end{DoxyCode}


Enable the RCC LSE CSS Event Line. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga45a0bf105427b24b377125346b2e597d}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_FALLING\_EDGE@{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_FALLING\_EDGE}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_FALLING\_EDGE@{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_FALLING\_EDGE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_FALLING\_EDGE}{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_FALLING\_EDGE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga45a0bf105427b24b377125346b2e597d} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(EXTI-\/>FTSR1,\ \mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_ga9b28da23df63fe2a235536edd669d8e9}{RCC\_EXTI\_LINE\_LSECSS}})}

\end{DoxyCode}


Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gafca78bb6fbfed8a31ef7ee030d424b50}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_IT@{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_IT}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_IT@{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_IT}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_IT}{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_IT}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gafca78bb6fbfed8a31ef7ee030d424b50} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(EXTI-\/>IMR1,\ \mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_ga9b28da23df63fe2a235536edd669d8e9}{RCC\_EXTI\_LINE\_LSECSS}})}

\end{DoxyCode}


Enable the RCC LSE CSS Extended Interrupt Line. 


\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga14487ed9c109cb494cae4a9762b7c294}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_EDGE@{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_EDGE}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_EDGE@{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_EDGE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_EDGE}{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_EDGE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga14487ed9c109cb494cae4a9762b7c294} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+EDGE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(EXTI-\/>RTSR1,\ \mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_ga9b28da23df63fe2a235536edd669d8e9}{RCC\_EXTI\_LINE\_LSECSS}})}

\end{DoxyCode}


Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga075e9194bfc08b5da32af130a74e7cb4}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE@{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE@{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE}{\_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga075e9194bfc08b5da32af130a74e7cb4} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \textcolor{keywordflow}{do}\ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_RISING\_EDGE();\ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \_\_HAL\_RCC\_LSECSS\_EXTI\_ENABLE\_FALLING\_EDGE();\ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \}\ \textcolor{keywordflow}{while}(0)}

\end{DoxyCode}


Enable the RCC LSE CSS Extended Interrupt Rising \& Falling Trigger. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gac5a7ed26daae142eb6cce551728ee88c}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_GENERATE\_SWIT@{\_\_HAL\_RCC\_LSECSS\_EXTI\_GENERATE\_SWIT}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_GENERATE\_SWIT@{\_\_HAL\_RCC\_LSECSS\_EXTI\_GENERATE\_SWIT}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_GENERATE\_SWIT}{\_\_HAL\_RCC\_LSECSS\_EXTI\_GENERATE\_SWIT}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gac5a7ed26daae142eb6cce551728ee88c} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+GENERATE\+\_\+\+SWIT(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(EXTI-\/>SWIER1,\ \mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_ga9b28da23df63fe2a235536edd669d8e9}{RCC\_EXTI\_LINE\_LSECSS}})}

\end{DoxyCode}


Generate a Software interrupt on the RCC LSE CSS EXTI line. 


\begin{DoxyRetVals}{Return values}
{\em None.} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga65fa248e1dd8c7258a50ba03c4e2ff85}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_LSECSS\_EXTI\_GET\_FLAG@{\_\_HAL\_RCC\_LSECSS\_EXTI\_GET\_FLAG}}
\index{\_\_HAL\_RCC\_LSECSS\_EXTI\_GET\_FLAG@{\_\_HAL\_RCC\_LSECSS\_EXTI\_GET\_FLAG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_LSECSS\_EXTI\_GET\_FLAG}{\_\_HAL\_RCC\_LSECSS\_EXTI\_GET\_FLAG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga65fa248e1dd8c7258a50ba03c4e2ff85} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LSECSS\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{(READ\_BIT(EXTI-\/>PR1,\ \mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_ga9b28da23df63fe2a235536edd669d8e9}{RCC\_EXTI\_LINE\_LSECSS}})\ ==\ \mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_ga9b28da23df63fe2a235536edd669d8e9}{RCC\_EXTI\_LINE\_LSECSS}})}

\end{DoxyCode}


Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 


\begin{DoxyRetVals}{Return values}
{\em EXTI} & RCC LSE CSS Line Status. \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga1b17f7d45a505cc6acce76a1a80d9aca}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL2\_CONFIG@{\_\_HAL\_RCC\_PLL2\_CONFIG}}
\index{\_\_HAL\_RCC\_PLL2\_CONFIG@{\_\_HAL\_RCC\_PLL2\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL2\_CONFIG}{\_\_HAL\_RCC\_PLL2\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga1b17f7d45a505cc6acce76a1a80d9aca} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+PLL2\+M\+\_\+\+\_\+}{, }\item[{}]{\+\_\+\+\_\+\+PLL2\+N\+\_\+\+\_\+}{, }\item[{}]{\+\_\+\+\_\+\+PLL2\+P\+\_\+\+\_\+}{, }\item[{}]{\+\_\+\+\_\+\+PLL2\+Q\+\_\+\+\_\+}{, }\item[{}]{\+\_\+\+\_\+\+PLL2\+R\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{keywordflow}{do}\{\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>PLLCKSELR,\ (\ RCC\_PLLCKSELR\_DIVM2)\ ,\ (\ (\_\_PLL2M\_\_)\ <<12U));\ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ WRITE\_REG\ (RCC-\/>PLL2DIVR\ ,\ (\ (((\_\_PLL2N\_\_)\ -\/\ 1U\ )\ \&\ RCC\_PLL2DIVR\_N2)\ |\ ((((\_\_PLL2P\_\_)\ -\/1U\ )\ <<\ 9U)\ \&\ RCC\_PLL2DIVR\_P2)\ |\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((((\_\_PLL2Q\_\_)\ -\/1U)\ <<\ 16U)\ \&\ RCC\_PLL2DIVR\_Q2)\ |\ ((((\_\_PLL2R\_\_)-\/\ 1U)\ <<\ 24U)\ \&\ RCC\_PLL2DIVR\_R2)));\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}(0)}

\end{DoxyCode}


Macro to configures the PLL2 multiplication and division factors. 

\begin{DoxyNote}{Note}
This function must be used only when PLL2 is disabled.
\end{DoxyNote}

\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+PLL2\+M\+\_\+\+\_\+} & specifies the division factor for PLL2 VCO input clock This parameter must be a number between 1 and 63. \\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
\end{DoxyNote}

\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+PLL2\+N\+\_\+\+\_\+} & specifies the multiplication factor for PLL2 VCO output clock This parameter must be a number between 4 and 512 or between 8 and 420(\texorpdfstring{$\ast$}{*}). \\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
You have to set the PLL2N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(\texorpdfstring{$\ast$}{*}) (when in wide VCO range)
\end{DoxyNote}

\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+PLL2\+P\+\_\+\+\_\+} & specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.\\
\hline
{\em \+\_\+\+\_\+\+PLL2\+Q\+\_\+\+\_\+} & specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.\\
\hline
{\em \+\_\+\+\_\+\+PLL2\+R\+\_\+\+\_\+} & specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.\\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
To insure an optimal behavior of the PLL when one of the post-\/divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVy\+EN) and assign lowest possible value to {\bfseries{PLL2P}}, {\bfseries{PLL2Q}} or {\bfseries{PLL2R}} parameters. 
\end{DoxyNote}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
(\texorpdfstring{$\ast$}{*}) \+: For stm32h7a3xx and stm32h7b3xx family lines. \Hypertarget{group___r_c_c_ex___exported___macros_ga1e44121d27a8d6096c170d4a2e7c1981}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL2\_DISABLE@{\_\_HAL\_RCC\_PLL2\_DISABLE}}
\index{\_\_HAL\_RCC\_PLL2\_DISABLE@{\_\_HAL\_RCC\_PLL2\_DISABLE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL2\_DISABLE}{\_\_HAL\_RCC\_PLL2\_DISABLE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga1e44121d27a8d6096c170d4a2e7c1981} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+\_\+\+DISABLE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(RCC-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga250f64c1041b823f2bd5dbbb4c54a2d5}{RCC\_CR\_PLL2ON}})}

\end{DoxyCode}
\Hypertarget{group___r_c_c_ex___exported___macros_gacc1a8ad328f57e3dcade01e5355e0add}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL2\_ENABLE@{\_\_HAL\_RCC\_PLL2\_ENABLE}}
\index{\_\_HAL\_RCC\_PLL2\_ENABLE@{\_\_HAL\_RCC\_PLL2\_ENABLE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL2\_ENABLE}{\_\_HAL\_RCC\_PLL2\_ENABLE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gacc1a8ad328f57e3dcade01e5355e0add} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+\_\+\+ENABLE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(RCC-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga250f64c1041b823f2bd5dbbb4c54a2d5}{RCC\_CR\_PLL2ON}})}

\end{DoxyCode}


Macros to enable or disable PLL2. 

\begin{DoxyNote}{Note}
After enabling PLL2, the application software should wait on PLL2\+RDY flag to be set indicating that PLL2 clock is stable and can be used as kernel clock source. 

PLL2 is disabled by hardware when entering STOP and STANDBY modes. 
\end{DoxyNote}
\Hypertarget{group___r_c_c_ex___exported___macros_ga88d12a5c64e4a820268b9f7f50d74179}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL2\_VCIRANGE@{\_\_HAL\_RCC\_PLL2\_VCIRANGE}}
\index{\_\_HAL\_RCC\_PLL2\_VCIRANGE@{\_\_HAL\_RCC\_PLL2\_VCIRANGE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL2\_VCIRANGE}{\_\_HAL\_RCC\_PLL2\_VCIRANGE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga88d12a5c64e4a820268b9f7f50d74179} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+\_\+\+VCIRANGE(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+VCIRange\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL2RGE,\ (\_\_RCC\_PLL2VCIRange\_\_))}

\end{DoxyCode}


Macro to select the PLL2 reference frequency range. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+VCIRange\+\_\+\+\_\+} & specifies the PLL2 input frequency range This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+PLL2\+VCIRANGE\+\_\+0\+: Range frequency is between 1 and 2 MHz \item RCC\+\_\+\+PLL2\+VCIRANGE\+\_\+1\+: Range frequency is between 2 and 4 MHz \item RCC\+\_\+\+PLL2\+VCIRANGE\+\_\+2\+: Range frequency is between 4 and 8 MHz \item RCC\+\_\+\+PLL2\+VCIRANGE\+\_\+3\+: Range frequency is between 8 and 16 MHz \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga5b448c0dab856525467ba9146db00432}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL2\_VCORANGE@{\_\_HAL\_RCC\_PLL2\_VCORANGE}}
\index{\_\_HAL\_RCC\_PLL2\_VCORANGE@{\_\_HAL\_RCC\_PLL2\_VCORANGE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL2\_VCORANGE}{\_\_HAL\_RCC\_PLL2\_VCORANGE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga5b448c0dab856525467ba9146db00432} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+\_\+\+VCORANGE(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+VCORange\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL2VCOSEL,\ (\_\_RCC\_PLL2VCORange\_\_))}

\end{DoxyCode}


Macro to select the PLL2 reference frequency range. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+VCORange\+\_\+\+\_\+} & Specifies the PLL2 input frequency range This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+PLL2\+VCOWIDE\+: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(\texorpdfstring{$\ast$}{*}) \item RCC\+\_\+\+PLL2\+VCOMEDIUM\+: Range frequency is between 150 and 420 MHz\end{DoxyItemize}
(\texorpdfstring{$\ast$}{*}) \+: For stm32h7a3xx and stm32h7b3xx family lines.\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga20869ea15ad0f090d4e3fcc217242474}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL2CLKOUT\_DISABLE@{\_\_HAL\_RCC\_PLL2CLKOUT\_DISABLE}}
\index{\_\_HAL\_RCC\_PLL2CLKOUT\_DISABLE@{\_\_HAL\_RCC\_PLL2CLKOUT\_DISABLE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL2CLKOUT\_DISABLE}{\_\_HAL\_RCC\_PLL2CLKOUT\_DISABLE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga20869ea15ad0f090d4e3fcc217242474} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+CLKOUT\+\_\+\+DISABLE(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+Clock\+Out\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(RCC-\/>PLLCFGR,\ (\_\_RCC\_PLL2ClockOut\_\_))}

\end{DoxyCode}
\Hypertarget{group___r_c_c_ex___exported___macros_gadee20de14af30b0f958fda51d852066b}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL2CLKOUT\_ENABLE@{\_\_HAL\_RCC\_PLL2CLKOUT\_ENABLE}}
\index{\_\_HAL\_RCC\_PLL2CLKOUT\_ENABLE@{\_\_HAL\_RCC\_PLL2CLKOUT\_ENABLE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL2CLKOUT\_ENABLE}{\_\_HAL\_RCC\_PLL2CLKOUT\_ENABLE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gadee20de14af30b0f958fda51d852066b} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+CLKOUT\+\_\+\+ENABLE(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+Clock\+Out\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(RCC-\/>PLLCFGR,\ (\_\_RCC\_PLL2ClockOut\_\_))}

\end{DoxyCode}


Enables or disables each clock output (PLL2\+\_\+\+P\+\_\+\+CLK, PLL2\+\_\+\+Q\+\_\+\+CLK, PLL2\+\_\+\+R\+\_\+\+CLK) 

\begin{DoxyNote}{Note}
Enabling/disabling those Clocks can be done only when the PLL2 is disabled, This is mainly used to save Power. 
\end{DoxyNote}

\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+Clock\+Out\+\_\+\+\_\+} & Specifies the PLL2 clock to be outputted This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+PLL2\+\_\+\+DIVP\+: This clock is used to generate peripherals clock up to 550MHZ(\texorpdfstring{$\ast$}{*}), 480MHZ(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}) or 280MHZ(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}) \item RCC\+\_\+\+PLL2\+\_\+\+DIVQ\+: This clock is used to generate peripherals clock up to 550MHZ(\texorpdfstring{$\ast$}{*}), 480MHZ(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}) or 280MHZ(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}) \item RCC\+\_\+\+PLL2\+\_\+\+DIVR\+: This clock is used to generate peripherals clock up to 550MHZ(\texorpdfstring{$\ast$}{*}), 480MHZ(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}) or 280MHZ(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*})\end{DoxyItemize}
(\texorpdfstring{$\ast$}{*}) \+: For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU\+\_\+\+FREQ\+\_\+\+BOOST flash option byte, 520MHZ otherwise. (\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}) \+: For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. (\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*})\+: For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gac2cb75d60618ffea824634490f9d81eb}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL2FRACN\_CONFIG@{\_\_HAL\_RCC\_PLL2FRACN\_CONFIG}}
\index{\_\_HAL\_RCC\_PLL2FRACN\_CONFIG@{\_\_HAL\_RCC\_PLL2FRACN\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL2FRACN\_CONFIG}{\_\_HAL\_RCC\_PLL2FRACN\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gac2cb75d60618ffea824634490f9d81eb} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+FRACN\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+FRACN\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>PLL2FRACR,\ RCC\_PLL2FRACR\_FRACN2,((uint32\_t)(\_\_RCC\_PLL2FRACN\_\_)\ <<\ RCC\_PLL2FRACR\_FRACN2\_Pos))}

\end{DoxyCode}


Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor. 

\begin{DoxyNote}{Note}
These bits can be written at any time, allowing dynamic fine-\/tuning of the PLL2 VCO
\end{DoxyNote}

\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+PLL2\+FRACN\+\_\+\+\_\+} & Specifies Fractional Part Of The Multiplication factor for PLL2 VCO It should be a value between 0 and 8191 \\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
Warning\+: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is\+: 192 to 836 MHz or 128 to 560 MHz(\texorpdfstring{$\ast$}{*}) if PLL2\+VCOSEL = 0 150 to 420 MHz if PLL2\+VCOSEL = 1.
\end{DoxyNote}
(\texorpdfstring{$\ast$}{*}) \+: For stm32h7a3xx and stm32h7b3xx family lines.


\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga320b2becbdbe9830622f1b96526a5d7b}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL2FRACN\_DISABLE@{\_\_HAL\_RCC\_PLL2FRACN\_DISABLE}}
\index{\_\_HAL\_RCC\_PLL2FRACN\_DISABLE@{\_\_HAL\_RCC\_PLL2FRACN\_DISABLE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL2FRACN\_DISABLE}{\_\_HAL\_RCC\_PLL2FRACN\_DISABLE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga320b2becbdbe9830622f1b96526a5d7b} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+FRACN\+\_\+\+DISABLE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL2FRACEN)}

\end{DoxyCode}
\Hypertarget{group___r_c_c_ex___exported___macros_ga25e0f4d0ef5f525a3c0c5c0a155d0ac6}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL2FRACN\_ENABLE@{\_\_HAL\_RCC\_PLL2FRACN\_ENABLE}}
\index{\_\_HAL\_RCC\_PLL2FRACN\_ENABLE@{\_\_HAL\_RCC\_PLL2FRACN\_ENABLE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL2FRACN\_ENABLE}{\_\_HAL\_RCC\_PLL2FRACN\_ENABLE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga25e0f4d0ef5f525a3c0c5c0a155d0ac6} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL2\+FRACN\+\_\+\+ENABLE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL2FRACEN)}

\end{DoxyCode}


Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO. 

\begin{DoxyNote}{Note}
Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 
\end{DoxyNote}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gac5020a08025c53436a32d77640786d5d}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL3\_CONFIG@{\_\_HAL\_RCC\_PLL3\_CONFIG}}
\index{\_\_HAL\_RCC\_PLL3\_CONFIG@{\_\_HAL\_RCC\_PLL3\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL3\_CONFIG}{\_\_HAL\_RCC\_PLL3\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gac5020a08025c53436a32d77640786d5d} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+PLL3\+M\+\_\+\+\_\+}{, }\item[{}]{\+\_\+\+\_\+\+PLL3\+N\+\_\+\+\_\+}{, }\item[{}]{\+\_\+\+\_\+\+PLL3\+P\+\_\+\+\_\+}{, }\item[{}]{\+\_\+\+\_\+\+PLL3\+Q\+\_\+\+\_\+}{, }\item[{}]{\+\_\+\+\_\+\+PLL3\+R\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{keywordflow}{do}\{\ MODIFY\_REG(RCC-\/>PLLCKSELR,\ (\ RCC\_PLLCKSELR\_DIVM3)\ ,\ (\ (\_\_PLL3M\_\_)\ <<20U));\ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ WRITE\_REG\ (RCC-\/>PLL3DIVR\ ,\ (\ (((\_\_PLL3N\_\_)\ -\/\ 1U\ )\ \&\ RCC\_PLL3DIVR\_N3)\ |\ ((((\_\_PLL3P\_\_)\ -\/1U\ )\ <<\ 9U)\ \&\ RCC\_PLL3DIVR\_P3)\ |\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((((\_\_PLL3Q\_\_)\ -\/1U)\ <<\ 16U)\ \&\ RCC\_PLL3DIVR\_Q3)\ |\ ((((\_\_PLL3R\_\_)\ -\/\ 1U)\ <<\ 24U)\ \&\ RCC\_PLL3DIVR\_R3)));\ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}(0)}

\end{DoxyCode}


Macro to configures the PLL3 multiplication and division factors. 

\begin{DoxyNote}{Note}
This function must be used only when PLL3 is disabled.
\end{DoxyNote}

\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+PLL3\+M\+\_\+\+\_\+} & specifies the division factor for PLL3 VCO input clock This parameter must be a number between 1 and 63. \\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
\end{DoxyNote}

\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+PLL3\+N\+\_\+\+\_\+} & specifies the multiplication factor for PLL3 VCO output clock This parameter must be a number between 4 and 512. \\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
You have to set the PLL3N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(\texorpdfstring{$\ast$}{*}) (when in wide VCO range)
\end{DoxyNote}

\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+PLL3\+P\+\_\+\+\_\+} & specifies the division factor for peripheral kernel clocks This parameter must be a number between 2 and 128 (where odd numbers not allowed)\\
\hline
{\em \+\_\+\+\_\+\+PLL3\+Q\+\_\+\+\_\+} & specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128\\
\hline
{\em \+\_\+\+\_\+\+PLL3\+R\+\_\+\+\_\+} & specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128\\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
To insure an optimal behavior of the PLL when one of the post-\/divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVy\+EN) and assign lowest possible value to {\bfseries{PLL3P}}, {\bfseries{PLL3Q}} or {\bfseries{PLL3R}} parameters. 
\end{DoxyNote}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
(\texorpdfstring{$\ast$}{*}) \+: For stm32h7a3xx and stm32h7b3xx family lines. \Hypertarget{group___r_c_c_ex___exported___macros_ga9eccd5f7fbfd12da15ba7d76d9a21d18}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL3\_DISABLE@{\_\_HAL\_RCC\_PLL3\_DISABLE}}
\index{\_\_HAL\_RCC\_PLL3\_DISABLE@{\_\_HAL\_RCC\_PLL3\_DISABLE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL3\_DISABLE}{\_\_HAL\_RCC\_PLL3\_DISABLE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga9eccd5f7fbfd12da15ba7d76d9a21d18} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+\_\+\+DISABLE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(RCC-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7e7f10468741ab47dc34808af0e49b2b}{RCC\_CR\_PLL3ON}})}

\end{DoxyCode}
\Hypertarget{group___r_c_c_ex___exported___macros_gac7c3a26323f470a939b021ad76f29518}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL3\_ENABLE@{\_\_HAL\_RCC\_PLL3\_ENABLE}}
\index{\_\_HAL\_RCC\_PLL3\_ENABLE@{\_\_HAL\_RCC\_PLL3\_ENABLE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL3\_ENABLE}{\_\_HAL\_RCC\_PLL3\_ENABLE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gac7c3a26323f470a939b021ad76f29518} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+\_\+\+ENABLE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(RCC-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7e7f10468741ab47dc34808af0e49b2b}{RCC\_CR\_PLL3ON}})}

\end{DoxyCode}


Macros to enable or disable the main PLL3. 

\begin{DoxyNote}{Note}
After enabling PLL3, the application software should wait on PLL3\+RDY flag to be set indicating that PLL3 clock is stable and can be used as kernel clock source. 

PLL3 is disabled by hardware when entering STOP and STANDBY modes. 
\end{DoxyNote}
\Hypertarget{group___r_c_c_ex___exported___macros_ga5825c7707fdbf1432a215fbf3ef4b766}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL3\_VCIRANGE@{\_\_HAL\_RCC\_PLL3\_VCIRANGE}}
\index{\_\_HAL\_RCC\_PLL3\_VCIRANGE@{\_\_HAL\_RCC\_PLL3\_VCIRANGE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL3\_VCIRANGE}{\_\_HAL\_RCC\_PLL3\_VCIRANGE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga5825c7707fdbf1432a215fbf3ef4b766} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+\_\+\+VCIRANGE(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+VCIRange\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL3RGE,\ (\_\_RCC\_PLL3VCIRange\_\_))}

\end{DoxyCode}


Macro to select the PLL3 reference frequency range. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+VCIRange\+\_\+\+\_\+} & specifies the PLL1 input frequency range This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+PLL3\+VCIRANGE\+\_\+0\+: Range frequency is between 1 and 2 MHz \item RCC\+\_\+\+PLL3\+VCIRANGE\+\_\+1\+: Range frequency is between 2 and 4 MHz \item RCC\+\_\+\+PLL3\+VCIRANGE\+\_\+2\+: Range frequency is between 4 and 8 MHz \item RCC\+\_\+\+PLL3\+VCIRANGE\+\_\+3\+: Range frequency is between 8 and 16 MHz \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga7c53c8f29406ecd9c45434db4b2af32d}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL3\_VCORANGE@{\_\_HAL\_RCC\_PLL3\_VCORANGE}}
\index{\_\_HAL\_RCC\_PLL3\_VCORANGE@{\_\_HAL\_RCC\_PLL3\_VCORANGE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL3\_VCORANGE}{\_\_HAL\_RCC\_PLL3\_VCORANGE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga7c53c8f29406ecd9c45434db4b2af32d} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+\_\+\+VCORANGE(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+VCORange\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL3VCOSEL,\ (\_\_RCC\_PLL3VCORange\_\_))}

\end{DoxyCode}


Macro to select the PLL3 reference frequency range. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+VCORange\+\_\+\+\_\+} & specifies the PLL1 input frequency range This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+PLL3\+VCOWIDE\+: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(\texorpdfstring{$\ast$}{*}) \item RCC\+\_\+\+PLL3\+VCOMEDIUM\+: Range frequency is between 150 and 420 MHz\end{DoxyItemize}
(\texorpdfstring{$\ast$}{*}) \+: For stm32h7a3xx and stm32h7b3xx family lines.\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga36d6e5c5786cab7644e5149d00f704c3}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL3CLKOUT\_DISABLE@{\_\_HAL\_RCC\_PLL3CLKOUT\_DISABLE}}
\index{\_\_HAL\_RCC\_PLL3CLKOUT\_DISABLE@{\_\_HAL\_RCC\_PLL3CLKOUT\_DISABLE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL3CLKOUT\_DISABLE}{\_\_HAL\_RCC\_PLL3CLKOUT\_DISABLE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga36d6e5c5786cab7644e5149d00f704c3} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+CLKOUT\+\_\+\+DISABLE(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+Clock\+Out\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(RCC-\/>PLLCFGR,\ (\_\_RCC\_PLL3ClockOut\_\_))}

\end{DoxyCode}
\Hypertarget{group___r_c_c_ex___exported___macros_ga44dba3c4e64245e760eb3e780096b4da}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL3CLKOUT\_ENABLE@{\_\_HAL\_RCC\_PLL3CLKOUT\_ENABLE}}
\index{\_\_HAL\_RCC\_PLL3CLKOUT\_ENABLE@{\_\_HAL\_RCC\_PLL3CLKOUT\_ENABLE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL3CLKOUT\_ENABLE}{\_\_HAL\_RCC\_PLL3CLKOUT\_ENABLE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga44dba3c4e64245e760eb3e780096b4da} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+CLKOUT\+\_\+\+ENABLE(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+Clock\+Out\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(RCC-\/>PLLCFGR,\ (\_\_RCC\_PLL3ClockOut\_\_))}

\end{DoxyCode}


Enables or disables each clock output (PLL3\+\_\+\+P\+\_\+\+CLK, PLL3\+\_\+\+Q\+\_\+\+CLK, PLL3\+\_\+\+R\+\_\+\+CLK) 

\begin{DoxyNote}{Note}
Enabling/disabling those Clocks can be done only when the PLL3 is disabled, This is mainly used to save Power. 
\end{DoxyNote}

\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+Clock\+Out\+\_\+\+\_\+} & specifies the PLL3 clock to be outputted This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+PLL3\+\_\+\+DIVP\+: This clock is used to generate peripherals clock up to 550MHZ(\texorpdfstring{$\ast$}{*}), 480MHZ(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}) or 280MHZ(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}) \item RCC\+\_\+\+PLL3\+\_\+\+DIVQ\+: This clock is used to generate peripherals clock up to 550MHZ(\texorpdfstring{$\ast$}{*}), 480MHZ(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}) or 280MHZ(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}) \item RCC\+\_\+\+PLL3\+\_\+\+DIVR\+: This clock is used to generate peripherals clock up to 550MHZ(\texorpdfstring{$\ast$}{*}), 480MHZ(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}) or 280MHZ(\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*})\end{DoxyItemize}
(\texorpdfstring{$\ast$}{*}) \+: For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU\+\_\+\+FREQ\+\_\+\+BOOST flash option byte, 520MHZ otherwise. (\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}) \+: For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. (\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*}\texorpdfstring{$\ast$}{*})\+: For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga3c6bb3051b93d8f3051ace7b1611c5c1}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL3FRACN\_CONFIG@{\_\_HAL\_RCC\_PLL3FRACN\_CONFIG}}
\index{\_\_HAL\_RCC\_PLL3FRACN\_CONFIG@{\_\_HAL\_RCC\_PLL3FRACN\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL3FRACN\_CONFIG}{\_\_HAL\_RCC\_PLL3FRACN\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga3c6bb3051b93d8f3051ace7b1611c5c1} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+FRACN\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+FRACN\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{MODIFY\_REG(RCC-\/>PLL3FRACR,\ RCC\_PLL3FRACR\_FRACN3,\ (uint32\_t)(\_\_RCC\_PLL3FRACN\_\_)\ <<\ RCC\_PLL3FRACR\_FRACN3\_Pos)}

\end{DoxyCode}


Macro to configures PLL3 clock Fractional Part of The Multiplication Factor. 

\begin{DoxyNote}{Note}
These bits can be written at any time, allowing dynamic fine-\/tuning of the PLL3 VCO
\end{DoxyNote}

\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+PLL3\+FRACN\+\_\+\+\_\+} & specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value between 0 and 8191 \\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
Warning\+: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is\+: 192 to 836 MHz or 128 to 560 MHz(\texorpdfstring{$\ast$}{*}) if PLL3\+VCOSEL = 0 150 to 420 MHz if PLL3\+VCOSEL = 1.
\end{DoxyNote}
(\texorpdfstring{$\ast$}{*}) \+: For stm32h7a3xx and stm32h7b3xx family lines.


\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga4a2fb65aefcf9fd35d55a5de8000173e}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL3FRACN\_DISABLE@{\_\_HAL\_RCC\_PLL3FRACN\_DISABLE}}
\index{\_\_HAL\_RCC\_PLL3FRACN\_DISABLE@{\_\_HAL\_RCC\_PLL3FRACN\_DISABLE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL3FRACN\_DISABLE}{\_\_HAL\_RCC\_PLL3FRACN\_DISABLE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga4a2fb65aefcf9fd35d55a5de8000173e} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+FRACN\+\_\+\+DISABLE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL3FRACEN)}

\end{DoxyCode}
\Hypertarget{group___r_c_c_ex___exported___macros_ga35af940f02bf692f69ca9cf2dd598f24}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_PLL3FRACN\_ENABLE@{\_\_HAL\_RCC\_PLL3FRACN\_ENABLE}}
\index{\_\_HAL\_RCC\_PLL3FRACN\_ENABLE@{\_\_HAL\_RCC\_PLL3FRACN\_ENABLE}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_PLL3FRACN\_ENABLE}{\_\_HAL\_RCC\_PLL3FRACN\_ENABLE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga35af940f02bf692f69ca9cf2dd598f24} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PLL3\+FRACN\+\_\+\+ENABLE(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{SET\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL3FRACEN)}

\end{DoxyCode}


Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO. 

\begin{DoxyNote}{Note}
Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 
\end{DoxyNote}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gae34a5e47c3e3a519bfca1f4313a88f9f}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_RNG\_CONFIG@{\_\_HAL\_RCC\_RNG\_CONFIG}}
\index{\_\_HAL\_RCC\_RNG\_CONFIG@{\_\_HAL\_RCC\_RNG\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_RNG\_CONFIG}{\_\_HAL\_RCC\_RNG\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gae34a5e47c3e3a519bfca1f4313a88f9f} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RNGCLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_RNGSEL,\ (uint32\_t)(\_\_RNGCLKSource\_\_))}

\end{DoxyCode}


macro to configure the RNG clock (RNGCLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RNGCLKSource\+\_\+\+\_\+} & specifies the RNG clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+RNGCLKSOURCE\+\_\+\+HSI48\+: HSI48 selected as RNG clock \item RCC\+\_\+\+RNGCLKSOURCE\+\_\+\+PLL\+: PLL1Q selected as RNG clock \item RCC\+\_\+\+RNGCLKSOURCE\+\_\+\+LSE\+: LSE selected as RNG clock \item RCC\+\_\+\+RNGCLKSOURCE\+\_\+\+LSI\+: LSI selected as RNG clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga0c98df7eb7d710df2bf05427a4a10bc7}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_SAI1\_CONFIG@{\_\_HAL\_RCC\_SAI1\_CONFIG}}
\index{\_\_HAL\_RCC\_SAI1\_CONFIG@{\_\_HAL\_RCC\_SAI1\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_SAI1\_CONFIG}{\_\_HAL\_RCC\_SAI1\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga0c98df7eb7d710df2bf05427a4a10bc7} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+SAI1\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SAI1SEL,\ (\_\_RCC\_SAI1CLKSource\_\_))}

\end{DoxyCode}


Macro to Configure the SAI1 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+SAI1\+CLKSource\+\_\+\+\_\+} & defines the SAI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SAI1\+CLKSOURCE\+\_\+\+PLL\+: SAI1 clock = PLL \item RCC\+\_\+\+SAI1\+CLKSOURCE\+\_\+\+PLL2\+: SAI1 clock = PLL2 \item RCC\+\_\+\+SAI1\+CLKSOURCE\+\_\+\+PLL3\+: SAI1 clock = PLL3 \item RCC\+\_\+\+SAI1\+CLKSOURCE\+\_\+\+OSC\+: SAI1 clock = OSC \item RCC\+\_\+\+SAI1\+CLKSOURCE\+\_\+\+PIN\+: SAI1 clock = External Clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga7754edd5cc00e691c5007f22d3a93d38}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_SDMMC\_CONFIG@{\_\_HAL\_RCC\_SDMMC\_CONFIG}}
\index{\_\_HAL\_RCC\_SDMMC\_CONFIG@{\_\_HAL\_RCC\_SDMMC\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_SDMMC\_CONFIG}{\_\_HAL\_RCC\_SDMMC\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga7754edd5cc00e691c5007f22d3a93d38} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+SDMMCCLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_SDMMCSEL,\ (uint32\_t)(\_\_SDMMCCLKSource\_\_))}

\end{DoxyCode}


Macro to configure the SDMMC clock. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+SDMMCCLKSource\+\_\+\+\_\+} & specifies clock source for SDMMC This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SDMMCCLKSOURCE\+\_\+\+PLL\+: PLLQ selected as SDMMC clock \item RCC\+\_\+\+SDMMCCLKSOURCE\+\_\+\+PLL2\+: PLL2R selected as SDMMC clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga6cf17efbf8f472437732901308320283}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_SPDIFRX\_CONFIG@{\_\_HAL\_RCC\_SPDIFRX\_CONFIG}}
\index{\_\_HAL\_RCC\_SPDIFRX\_CONFIG@{\_\_HAL\_RCC\_SPDIFRX\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_SPDIFRX\_CONFIG}{\_\_HAL\_RCC\_SPDIFRX\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga6cf17efbf8f472437732901308320283} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPDIFRX\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+SPDIFCLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SPDIFSEL,\ (\_\_RCC\_SPDIFCLKSource\_\_))}

\end{DoxyCode}


Macro to Configure the SPDIFRX clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+SPDIFCLKSource\+\_\+\+\_\+} & defines the SPDIFRX clock source. This clock is derived from system PLL, PLL2, PLL3, or internal OSC clock This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPDIFRXCLKSOURCE\+\_\+\+PLL\+: SPDIFRX clock = PLL \item RCC\+\_\+\+SPDIFRXCLKSOURCE\+\_\+\+PLL2\+: SPDIFRX clock = PLL2 \item RCC\+\_\+\+SPDIFRXCLKSOURCE\+\_\+\+PLL3\+: SPDIFRX clock = PLL3 \item RCC\+\_\+\+SPDIFRXCLKSOURCE\+\_\+\+HSI\+: SPDIFRX clock = HSI \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga8da215b69bc3712d5bb359c66198d374}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_SPI123\_CONFIG@{\_\_HAL\_RCC\_SPI123\_CONFIG}}
\index{\_\_HAL\_RCC\_SPI123\_CONFIG@{\_\_HAL\_RCC\_SPI123\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_SPI123\_CONFIG}{\_\_HAL\_RCC\_SPI123\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga8da215b69bc3712d5bb359c66198d374} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI123\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+SPI123\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SPI123SEL,\ (\_\_RCC\_SPI123CLKSource\_\_))}

\end{DoxyCode}


Macro to Configure the SPI1/2/3 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+SPI123\+CLKSource\+\_\+\+\_\+} & defines the SPI1/2/3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+PLL\+: SPI1/2/3 clock = PLL \item RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+PLL2\+: SPI1/2/3 clock = PLL2 \item RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+PLL3\+: SPI1/2/3 clock = PLL3 \item RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+CLKP\+: SPI1/2/3 clock = CLKP \item RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+PIN\+: SPI1/2/3 clock = External Clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga9b531a40f565975ef8901b48afddf1cc}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_SPI1\_CONFIG@{\_\_HAL\_RCC\_SPI1\_CONFIG}}
\index{\_\_HAL\_RCC\_SPI1\_CONFIG@{\_\_HAL\_RCC\_SPI1\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_SPI1\_CONFIG}{\_\_HAL\_RCC\_SPI1\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga9b531a40f565975ef8901b48afddf1cc} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+CONFIG~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga8da215b69bc3712d5bb359c66198d374}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI123\+\_\+\+CONFIG}}}



Macro to Configure the SPI1 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+SPI1\+CLKSource\+\_\+\+\_\+} & defines the SPI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI1\+CLKSOURCE\+\_\+\+PLL\+: SPI1 clock = PLL \item RCC\+\_\+\+SPI1\+CLKSOURCE\+\_\+\+PLL2\+: SPI1 clock = PLL2 \item RCC\+\_\+\+SPI1\+CLKSOURCE\+\_\+\+PLL3\+: SPI1 clock = PLL3 \item RCC\+\_\+\+SPI1\+CLKSOURCE\+\_\+\+CLKP\+: SPI1 clock = CLKP \item RCC\+\_\+\+SPI1\+CLKSOURCE\+\_\+\+PIN\+: SPI1 clock = External Clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga03aafcdc3a862d9f10a5d1fcce4b549e}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_SPI2\_CONFIG@{\_\_HAL\_RCC\_SPI2\_CONFIG}}
\index{\_\_HAL\_RCC\_SPI2\_CONFIG@{\_\_HAL\_RCC\_SPI2\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_SPI2\_CONFIG}{\_\_HAL\_RCC\_SPI2\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga03aafcdc3a862d9f10a5d1fcce4b549e} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+CONFIG~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga8da215b69bc3712d5bb359c66198d374}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI123\+\_\+\+CONFIG}}}



Macro to Configure the SPI2 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+SPI2\+CLKSource\+\_\+\+\_\+} & defines the SPI2 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+PLL\+: SPI2 clock = PLL \item RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+PLL2\+: SPI2 clock = PLL2 \item RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+PLL3\+: SPI2 clock = PLL3 \item RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+CLKP\+: SPI2 clock = CLKP \item RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+PIN\+: SPI2 clock = External Clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga72e45b0673f5829c390032f8bbb24f17}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_SPI3\_CONFIG@{\_\_HAL\_RCC\_SPI3\_CONFIG}}
\index{\_\_HAL\_RCC\_SPI3\_CONFIG@{\_\_HAL\_RCC\_SPI3\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_SPI3\_CONFIG}{\_\_HAL\_RCC\_SPI3\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga72e45b0673f5829c390032f8bbb24f17} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+CONFIG~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga8da215b69bc3712d5bb359c66198d374}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI123\+\_\+\+CONFIG}}}



Macro to Configure the SPI3 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+SPI3\+CLKSource\+\_\+\+\_\+} & defines the SPI3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI3\+CLKSOURCE\+\_\+\+PLL\+: SPI3 clock = PLL \item RCC\+\_\+\+SPI3\+CLKSOURCE\+\_\+\+PLL2\+: SPI3 clock = PLL2 \item RCC\+\_\+\+SPI3\+CLKSOURCE\+\_\+\+PLL3\+: SPI3 clock = PLL3 \item RCC\+\_\+\+SPI3\+CLKSOURCE\+\_\+\+CLKP\+: SPI3 clock = CLKP \item RCC\+\_\+\+SPI3\+CLKSOURCE\+\_\+\+PIN\+: SPI3 clock = External Clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_gaecfe51f0d81f0130e1a5a06408320b72}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_SPI45\_CONFIG@{\_\_HAL\_RCC\_SPI45\_CONFIG}}
\index{\_\_HAL\_RCC\_SPI45\_CONFIG@{\_\_HAL\_RCC\_SPI45\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_SPI45\_CONFIG}{\_\_HAL\_RCC\_SPI45\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gaecfe51f0d81f0130e1a5a06408320b72} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI45\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+SPI45\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SPI45SEL,\ (\_\_RCC\_SPI45CLKSource\_\_))}

\end{DoxyCode}


Macro to Configure the SPI4/5 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+SPI45\+CLKSource\+\_\+\+\_\+} & defines the SPI4/5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI45\+CLKSOURCE\+\_\+\+D2\+PCLK2\+:SPI4/5 clock = D2\+PCLK2 \item RCC\+\_\+\+SPI45\+CLKSOURCE\+\_\+\+PLL2\+: SPI4/5 clock = PLL2 \item RCC\+\_\+\+SPI45\+CLKSOURCE\+\_\+\+PLL3\+: SPI4/5 clock = PLL3 \item RCC\+\_\+\+SPI45\+CLKSOURCE\+\_\+\+HSI\+: SPI4/5 clock = HSI \item RCC\+\_\+\+SPI45\+CLKSOURCE\+\_\+\+CSI\+: SPI4/5 clock = CSI \item RCC\+\_\+\+SPI45\+CLKSOURCE\+\_\+\+HSE\+: SPI4/5 clock = HSE \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga04806afde06b2bc3b4e409b81fce5c41}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_SPI4\_CONFIG@{\_\_HAL\_RCC\_SPI4\_CONFIG}}
\index{\_\_HAL\_RCC\_SPI4\_CONFIG@{\_\_HAL\_RCC\_SPI4\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_SPI4\_CONFIG}{\_\_HAL\_RCC\_SPI4\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga04806afde06b2bc3b4e409b81fce5c41} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+CONFIG~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_gaecfe51f0d81f0130e1a5a06408320b72}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI45\+\_\+\+CONFIG}}}



Macro to Configure the SPI4 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+SPI4\+CLKSource\+\_\+\+\_\+} & defines the SPI4 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI4\+CLKSOURCE\+\_\+\+D2\+PCLK2\+:SPI4 clock = D2\+PCLK2 \item RCC\+\_\+\+SPI4\+CLKSOURCE\+\_\+\+PLL2\+: SPI4 clock = PLL2 \item RCC\+\_\+\+SPI4\+CLKSOURCE\+\_\+\+PLL3\+: SPI4 clock = PLL3 \item RCC\+\_\+\+SPI4\+CLKSOURCE\+\_\+\+HSI\+: SPI4 clock = HSI \item RCC\+\_\+\+SPI4\+CLKSOURCE\+\_\+\+CSI\+: SPI4 clock = CSI \item RCC\+\_\+\+SPI4\+CLKSOURCE\+\_\+\+HSE\+: SPI4 clock = HSE \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga14c138363b18bdee29cbb3ec82594b92}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_SPI5\_CONFIG@{\_\_HAL\_RCC\_SPI5\_CONFIG}}
\index{\_\_HAL\_RCC\_SPI5\_CONFIG@{\_\_HAL\_RCC\_SPI5\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_SPI5\_CONFIG}{\_\_HAL\_RCC\_SPI5\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga14c138363b18bdee29cbb3ec82594b92} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+CONFIG~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_gaecfe51f0d81f0130e1a5a06408320b72}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI45\+\_\+\+CONFIG}}}



Macro to Configure the SPI5 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+SPI5\+CLKSource\+\_\+\+\_\+} & defines the SPI5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI5\+CLKSOURCE\+\_\+\+D2\+PCLK2\+:SPI5 clock = D2\+PCLK2 \item RCC\+\_\+\+SPI5\+CLKSOURCE\+\_\+\+PLL2\+: SPI5 clock = PLL2 \item RCC\+\_\+\+SPI5\+CLKSOURCE\+\_\+\+PLL3\+: SPI5 clock = PLL3 \item RCC\+\_\+\+SPI5\+CLKSOURCE\+\_\+\+HSI\+: SPI5 clock = HSI \item RCC\+\_\+\+SPI5\+CLKSOURCE\+\_\+\+CSI\+: SPI5 clock = CSI \item RCC\+\_\+\+SPI5\+CLKSOURCE\+\_\+\+HSE\+: SPI5 clock = HSE \end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga1170019b0ed2e1301d2284c2af149f33}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_SPI6\_CONFIG@{\_\_HAL\_RCC\_SPI6\_CONFIG}}
\index{\_\_HAL\_RCC\_SPI6\_CONFIG@{\_\_HAL\_RCC\_SPI6\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_SPI6\_CONFIG}{\_\_HAL\_RCC\_SPI6\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga1170019b0ed2e1301d2284c2af149f33} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+RCC\+\_\+\+SPI6\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_SPI6SEL,\ (\_\_RCC\_SPI6CLKSource\_\_))}

\end{DoxyCode}


Macro to Configure the SPI6 clock source. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+RCC\+\_\+\+SPI6\+CLKSource\+\_\+\+\_\+} & defines the SPI6 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+D3\+PCLK1\+:SPI6 clock = D2\+PCLK1 \item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+PLL2\+: SPI6 clock = PLL2 \item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+PLL3\+: SPI6 clock = PLL3 \item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+HSI\+: SPI6 clock = HSI \item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+CSI\+: SPI6 clock = CSI \item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+HSE\+: SPI6 clock = HSE \item RCC\+\_\+\+SPI6\+CLKSOURCE\+\_\+\+PIN\+: SPI6 clock = I2\+S\+\_\+\+CKIN (\texorpdfstring{$\ast$}{*})\end{DoxyItemize}
\\
\hline
\end{DoxyParams}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
(\texorpdfstring{$\ast$}{*}) \+: Available on stm32h7a3xx and stm32h7b3xx family lines. \Hypertarget{group___r_c_c_ex___exported___macros_gac23e7b662783a7131e3e892ff0c21f06}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_SWPMI1\_CONFIG@{\_\_HAL\_RCC\_SWPMI1\_CONFIG}}
\index{\_\_HAL\_RCC\_SWPMI1\_CONFIG@{\_\_HAL\_RCC\_SWPMI1\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_SWPMI1\_CONFIG}{\_\_HAL\_RCC\_SWPMI1\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gac23e7b662783a7131e3e892ff0c21f06} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+SWPMI1\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SWPSEL,\ (uint32\_t)(\_\_SWPMI1CLKSource\_\_))}

\end{DoxyCode}


Macro to configure the SWPMI1 clock. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+SWPMI1\+CLKSource\+\_\+\+\_\+} & specifies the SWPMI1 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+SWPMI1\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: D2\+PCLK1 Clock selected as SWPMI1 clock \item RCC\+\_\+\+SWPMI1\+CLKSOURCE\+\_\+\+HSI\+: HSI Clock selected as SWPMI1 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga292ca7c84f192778314125ed6d7c8333}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_TIMCLKPRESCALER@{\_\_HAL\_RCC\_TIMCLKPRESCALER}}
\index{\_\_HAL\_RCC\_TIMCLKPRESCALER@{\_\_HAL\_RCC\_TIMCLKPRESCALER}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_TIMCLKPRESCALER}{\_\_HAL\_RCC\_TIMCLKPRESCALER}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga292ca7c84f192778314125ed6d7c8333} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIMCLKPRESCALER(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+PRESC\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{keywordflow}{do}\ \{RCC-\/>CFGR\ \&=\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6d6448d5ee420f8cc87b22b1201f5be2}{RCC\_CFGR\_TIMPRE}});\(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ RCC-\/>CFGR\ |=\ (\_\_PRESC\_\_);\ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\textcolor{keywordflow}{while}(0)}

\end{DoxyCode}


Macro to configure the Timers clocks prescalers. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+PRESC\+\_\+\+\_\+} & specifies the Timers clocks prescalers selection This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+TIMPRES\+\_\+\+DESACTIVATED\+: The Timers kernels clocks prescaler is equal to rcc\+\_\+hclk1 if D2\+PPREx is corresponding to division by 1 or 2, else it is equal to 2 x Frcc\+\_\+pclkx\+\_\+d2 (default after reset) \item RCC\+\_\+\+TIMPRES\+\_\+\+ACTIVATED\+: The Timers kernels clocks prescaler is equal to rcc\+\_\+hclk1 if D2\+PPREx is corresponding to division by 1, 2 or 4, else it is equal to 4 x Frcc\+\_\+pclkx\+\_\+d2 \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga711b187525b8b788b9f0ca968b1bd648}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_UART4\_CONFIG@{\_\_HAL\_RCC\_UART4\_CONFIG}}
\index{\_\_HAL\_RCC\_UART4\_CONFIG@{\_\_HAL\_RCC\_UART4\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_UART4\_CONFIG}{\_\_HAL\_RCC\_UART4\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga711b187525b8b788b9f0ca968b1bd648} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CONFIG~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}}



macro to configure the UART4 clock (UART4\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+UART4\+CLKSource\+\_\+\+\_\+} & specifies the UART4 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+UART4\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as UART4 clock \item RCC\+\_\+\+UART4\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as UART4 clock \item RCC\+\_\+\+UART4\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as UART4 clock \item RCC\+\_\+\+UART4\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as UART4 clock \item RCC\+\_\+\+UART4\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as UART4 clock \item RCC\+\_\+\+UART4\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as UART4 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_gae6c043e0b4091279d4db065b38b801b1}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_UART5\_CONFIG@{\_\_HAL\_RCC\_UART5\_CONFIG}}
\index{\_\_HAL\_RCC\_UART5\_CONFIG@{\_\_HAL\_RCC\_UART5\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_UART5\_CONFIG}{\_\_HAL\_RCC\_UART5\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gae6c043e0b4091279d4db065b38b801b1} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CONFIG~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}}



macro to configure the UART5 clock (UART5\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+UART5\+CLKSource\+\_\+\+\_\+} & specifies the UART5 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+UART5\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as UART5 clock \item RCC\+\_\+\+UART5\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as UART5 clock \item RCC\+\_\+\+UART5\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as UART5 clock \item RCC\+\_\+\+UART5\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as UART5 clock \item RCC\+\_\+\+UART5\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as UART5 clock \item RCC\+\_\+\+UART5\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as UART5 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga60bd7f1550266967e3f87a85afbddb7a}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_UART7\_CONFIG@{\_\_HAL\_RCC\_UART7\_CONFIG}}
\index{\_\_HAL\_RCC\_UART7\_CONFIG@{\_\_HAL\_RCC\_UART7\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_UART7\_CONFIG}{\_\_HAL\_RCC\_UART7\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga60bd7f1550266967e3f87a85afbddb7a} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+CONFIG~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}}



macro to configure the UART5 clock (UART7\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+UART7\+CLKSource\+\_\+\+\_\+} & specifies the UART7 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+UART7\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as UART7 clock \item RCC\+\_\+\+UART7\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as UART7 clock \item RCC\+\_\+\+UART7\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as UART7 clock \item RCC\+\_\+\+UART7\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as UART7 clock \item RCC\+\_\+\+UART7\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as UART7 clock \item RCC\+\_\+\+UART7\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as UART7 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga492a06425e99e15b064d5278cf319722}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_UART8\_CONFIG@{\_\_HAL\_RCC\_UART8\_CONFIG}}
\index{\_\_HAL\_RCC\_UART8\_CONFIG@{\_\_HAL\_RCC\_UART8\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_UART8\_CONFIG}{\_\_HAL\_RCC\_UART8\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga492a06425e99e15b064d5278cf319722} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+CONFIG~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}}



macro to configure the UART8 clock (UART8\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+UART8\+CLKSource\+\_\+\+\_\+} & specifies the UART8 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+UART8\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as UART8 clock \item RCC\+\_\+\+UART8\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as UART8 clock \item RCC\+\_\+\+UART8\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as UART8 clock \item RCC\+\_\+\+UART8\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as UART8 clock \item RCC\+\_\+\+UART8\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as UART8 clock \item RCC\+\_\+\+UART8\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as UART8 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga5d331d1d7b05a87debf939ff00d961d5}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_USART16910\_CONFIG@{\_\_HAL\_RCC\_USART16910\_CONFIG}}
\index{\_\_HAL\_RCC\_USART16910\_CONFIG@{\_\_HAL\_RCC\_USART16910\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_USART16910\_CONFIG}{\_\_HAL\_RCC\_USART16910\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga5d331d1d7b05a87debf939ff00d961d5} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART16910\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+USART16910\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>D2CCIP2R,\ RCC\_D2CCIP2R\_USART16910SEL,\ (uint32\_t)(\_\_USART16910CLKSource\_\_))}

\end{DoxyCode}


macro to configure the USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock (USART16\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+USART16910\+CLKSource\+\_\+\+\_\+} & specifies the USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USART16\+CLKSOURCE\+\_\+\+D2\+PCLK2\+: APB2 Clock selected as USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+USART16\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+USART16\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+USART16\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+USART16\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock \item RCC\+\_\+\+USART16\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as USART1/6/9\texorpdfstring{$\ast$}{*} /10\texorpdfstring{$\ast$}{*} clock\end{DoxyItemize}
(\texorpdfstring{$\ast$}{*}) \+: Available on some STM32\+H7 lines only. \\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga5c9ff3bd1509df21975b5a86202efd52}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_USART1\_CONFIG@{\_\_HAL\_RCC\_USART1\_CONFIG}}
\index{\_\_HAL\_RCC\_USART1\_CONFIG@{\_\_HAL\_RCC\_USART1\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_USART1\_CONFIG}{\_\_HAL\_RCC\_USART1\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga5c9ff3bd1509df21975b5a86202efd52} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+CONFIG~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART16\+\_\+\+CONFIG}



macro to configure the USART1 clock (USART1\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+USART1\+CLKSource\+\_\+\+\_\+} & specifies the USART1 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USART1\+CLKSOURCE\+\_\+\+D2\+PCLK2\+: APB2 Clock selected as USART1 clock \item RCC\+\_\+\+USART1\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as USART1 clock \item RCC\+\_\+\+USART1\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as USART1 clock \item RCC\+\_\+\+USART1\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as USART1 clock \item RCC\+\_\+\+USART1\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as USART1 clock \item RCC\+\_\+\+USART1\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as USART1 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_USART234578\_CONFIG@{\_\_HAL\_RCC\_USART234578\_CONFIG}}
\index{\_\_HAL\_RCC\_USART234578\_CONFIG@{\_\_HAL\_RCC\_USART234578\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_USART234578\_CONFIG}{\_\_HAL\_RCC\_USART234578\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+USART234578\+CLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_USART234578SEL,\ (uint32\_t)(\_\_USART234578CLKSource\_\_))}

\end{DoxyCode}


macro to configure the USART234578 clock (USART234578\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+USART234578\+CLKSource\+\_\+\+\_\+} & specifies the USART2/3/4/5/7/8 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USART234578\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as USART2/3/4/5/7/8 clock \item RCC\+\_\+\+USART234578\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as USART2/3/4/5/7/8 clock \item RCC\+\_\+\+USART234578\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as USART2/3/4/5/7/8 clock \item RCC\+\_\+\+USART234578\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as USART2/3/4/5/7/8 clock \item RCC\+\_\+\+USART234578\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as USART2/3/4/5/7/8 clock \item RCC\+\_\+\+USART234578\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as USART2/3/4/5/7/8 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_gaba22cefcb74b384a2e2fb3d2c51fae54}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_USART2\_CONFIG@{\_\_HAL\_RCC\_USART2\_CONFIG}}
\index{\_\_HAL\_RCC\_USART2\_CONFIG@{\_\_HAL\_RCC\_USART2\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_USART2\_CONFIG}{\_\_HAL\_RCC\_USART2\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gaba22cefcb74b384a2e2fb3d2c51fae54} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+CONFIG~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}}



macro to configure the USART2 clock (USART2\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+USART2\+CLKSource\+\_\+\+\_\+} & specifies the USART2 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as USART2 clock \item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as USART2 clock \item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as USART2 clock \item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as USART2 clock \item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as USART2 clock \item RCC\+\_\+\+USART2\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as USART2 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_gac1a20f806bcd2ec6cc781bab1d99e5b5}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_USART3\_CONFIG@{\_\_HAL\_RCC\_USART3\_CONFIG}}
\index{\_\_HAL\_RCC\_USART3\_CONFIG@{\_\_HAL\_RCC\_USART3\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_USART3\_CONFIG}{\_\_HAL\_RCC\_USART3\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_gac1a20f806bcd2ec6cc781bab1d99e5b5} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+CONFIG~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga67f80d0a54e4800370619e3247e3ae01}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART234578\+\_\+\+CONFIG}}}



macro to configure the USART3 clock (USART3\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+USART3\+CLKSource\+\_\+\+\_\+} & specifies the USART3 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USART3\+CLKSOURCE\+\_\+\+D2\+PCLK1\+: APB1 Clock selected as USART3 clock \item RCC\+\_\+\+USART3\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as USART3 clock \item RCC\+\_\+\+USART3\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as USART3 clock \item RCC\+\_\+\+USART3\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as USART3 clock \item RCC\+\_\+\+USART3\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as USART3 clock \item RCC\+\_\+\+USART3\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as USART3 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga28d9b1a1ce7ec3639b1d02ca10104704}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_USART6\_CONFIG@{\_\_HAL\_RCC\_USART6\_CONFIG}}
\index{\_\_HAL\_RCC\_USART6\_CONFIG@{\_\_HAL\_RCC\_USART6\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_USART6\_CONFIG}{\_\_HAL\_RCC\_USART6\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga28d9b1a1ce7ec3639b1d02ca10104704} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+CONFIG~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART16\+\_\+\+CONFIG}



macro to configure the USART6 clock (USART6\+CLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+USART6\+CLKSource\+\_\+\+\_\+} & specifies the USART6 clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USART6\+CLKSOURCE\+\_\+\+D2\+PCLK2\+: APB2 Clock selected as USART6 clock \item RCC\+\_\+\+USART6\+CLKSOURCE\+\_\+\+PLL2\+: PLL2\+\_\+Q Clock selected as USART6 clock \item RCC\+\_\+\+USART6\+CLKSOURCE\+\_\+\+PLL3\+: PLL3\+\_\+Q Clock selected as USART6 clock \item RCC\+\_\+\+USART6\+CLKSOURCE\+\_\+\+HSI\+: HSI selected as USART6 clock \item RCC\+\_\+\+USART6\+CLKSOURCE\+\_\+\+CSI\+: CSI Clock selected as USART6 clock \item RCC\+\_\+\+USART6\+CLKSOURCE\+\_\+\+LSE\+: LSE selected as USART6 clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga1c690ec86648d92efb97d2598a0cb2f1}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!\_\_HAL\_RCC\_USB\_CONFIG@{\_\_HAL\_RCC\_USB\_CONFIG}}
\index{\_\_HAL\_RCC\_USB\_CONFIG@{\_\_HAL\_RCC\_USB\_CONFIG}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_HAL\_RCC\_USB\_CONFIG}{\_\_HAL\_RCC\_USB\_CONFIG}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga1c690ec86648d92efb97d2598a0cb2f1} 
\#define \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+CONFIG(\begin{DoxyParamCaption}\item[{}]{\+\_\+\+\_\+\+USBCLKSource\+\_\+\+\_\+}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MODIFY\_REG(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_USBSEL,\ (uint32\_t)(\_\_USBCLKSource\_\_))}

\end{DoxyCode}


Macro to configure the USB clock (USBCLK). 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+USBCLKSource\+\_\+\+\_\+} & specifies the USB clock source. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item RCC\+\_\+\+USBCLKSOURCE\+\_\+\+PLL\+: PLL1Q selected as USB clock \item RCC\+\_\+\+USBCLKSOURCE\+\_\+\+PLL3\+: PLL3Q Clock selected as USB clock \item RCC\+\_\+\+USBCLKSOURCE\+\_\+\+HSI48\+: RC48 MHZ Clock selected as USB clock \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\Hypertarget{group___r_c_c_ex___exported___macros_ga39626ad9573958c96dccc66d13b1b6fe}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!RCC\_CRS\_FLAG\_ERROR\_MASK@{RCC\_CRS\_FLAG\_ERROR\_MASK}}
\index{RCC\_CRS\_FLAG\_ERROR\_MASK@{RCC\_CRS\_FLAG\_ERROR\_MASK}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{RCC\_CRS\_FLAG\_ERROR\_MASK}{RCC\_CRS\_FLAG\_ERROR\_MASK}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga39626ad9573958c96dccc66d13b1b6fe} 
\#define RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+ERROR\+\_\+\+MASK~((uint32\+\_\+t)(\mbox{\hyperlink{group___r_c_c_ex___c_r_s___flags_ga4c4c324494f9c6469e53d225242c73d4}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+TRIMOVF}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___r_c_c_ex___c_r_s___flags_gad49f59e34225920835b69a34f1b4c02b}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCERR}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___r_c_c_ex___c_r_s___flags_ga78549e9f343ad843d6e5d45b4e08433c}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCMISS}}))}



Clear the CRS specified FLAG. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+FLAG\+\_\+\+\_\+} & specifies the flag to clear. This parameter can be one of the following values\+: \begin{DoxyItemize}
\item \doxylink{group___r_c_c_ex___c_r_s___flags_ga27e1ae14c7854ca42faf5379bea5ac39}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCOK} SYNC event OK \item \doxylink{group___r_c_c_ex___c_r_s___flags_ga244c3ca47b8099a79212ab10d8e823c9}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCWARN} SYNC warning \item \doxylink{group___r_c_c_ex___c_r_s___flags_ga92be7705ece62c427a262355305527fa}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+ERR} Error \item \doxylink{group___r_c_c_ex___c_r_s___flags_ga10697d7c12b710c52c26db522c11986b}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+ESYNC} Expected SYNC \item \doxylink{group___r_c_c_ex___c_r_s___flags_ga4c4c324494f9c6469e53d225242c73d4}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+TRIMOVF} Trimming overflow or underflow \item \doxylink{group___r_c_c_ex___c_r_s___flags_gad49f59e34225920835b69a34f1b4c02b}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCERR} SYNC error \item \doxylink{group___r_c_c_ex___c_r_s___flags_ga78549e9f343ad843d6e5d45b4e08433c}{RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCMISS} SYNC missed \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\begin{DoxyNote}{Note}
RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+ERR clears RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+TRIMOVF, RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCERR, RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+SYNCMISS and consequently RCC\+\_\+\+CRS\+\_\+\+FLAG\+\_\+\+ERR 
\end{DoxyNote}

\begin{DoxyRetVals}{Return values}
{\em None} & \\
\hline
\end{DoxyRetVals}
\Hypertarget{group___r_c_c_ex___exported___macros_ga4c5b57880a8c7e917998d0c6a73351fb}\index{RCCEx Exported Macros@{RCCEx Exported Macros}!RCC\_CRS\_IT\_ERROR\_MASK@{RCC\_CRS\_IT\_ERROR\_MASK}}
\index{RCC\_CRS\_IT\_ERROR\_MASK@{RCC\_CRS\_IT\_ERROR\_MASK}!RCCEx Exported Macros@{RCCEx Exported Macros}}
\doxysubsubsubsubsection{\texorpdfstring{RCC\_CRS\_IT\_ERROR\_MASK}{RCC\_CRS\_IT\_ERROR\_MASK}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___exported___macros_ga4c5b57880a8c7e917998d0c6a73351fb} 
\#define RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+ERROR\+\_\+\+MASK~((uint32\+\_\+t)(\mbox{\hyperlink{group___r_c_c_ex___c_r_s___interrupt___sources_ga031f913312b8af1f38dc7c5adcd716f1}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+TRIMOVF}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___r_c_c_ex___c_r_s___interrupt___sources_gaf464654bbdfda5b86982fc4aa5b5a031}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCERR}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___r_c_c_ex___c_r_s___interrupt___sources_gac6b25a96e779b2f7ee3223101109ee33}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCMISS}}))}



Clear the CRS interrupt pending bits. 


\begin{DoxyParams}{Parameters}
{\em \+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+} & specifies the interrupt pending bit to clear. This parameter can be any combination of the following values\+: \begin{DoxyItemize}
\item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga772a7eb77eaea0622fb3e3b20275a37f}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCOK} SYNC event OK interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga8b9e2cbfa3fd8d7c18f81685c24a394f}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCWARN} SYNC warning interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga01a198f277ff33e6fd5a9c2a6ad908b9}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+ERR} Synchronization or trimming error interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_gadf2de3907d21dfaea6b2444d66adfe13}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+ESYNC} Expected SYNC interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_ga031f913312b8af1f38dc7c5adcd716f1}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+TRIMOVF} Trimming overflow or underflow interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_gaf464654bbdfda5b86982fc4aa5b5a031}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCERR} SYNC error interrupt \item \doxylink{group___r_c_c_ex___c_r_s___interrupt___sources_gac6b25a96e779b2f7ee3223101109ee33}{RCC\+\_\+\+CRS\+\_\+\+IT\+\_\+\+SYNCMISS} SYNC missed interrupt \end{DoxyItemize}
\\
\hline
\end{DoxyParams}
\input{group___r_c_c_ex___c_r_s___extended___features}
